Fabrication of amorphous silicon nanoribbons by atomic force microscope tip induced local oxidation for thin film device applications

WOSInternational audienceWe demonstrate the feasibility of induced local oxidation of amorphous silicon by atomic force microscopy. The resulting local oxide is used as mask for the elaboration of thin film silicon resistor. A thin amorphous silicon layer deposited on a glass substrate is locally oxidized following narrow continuous lines. The corresponding oxide line is then used as mask during plasma etching of the amorphous layer leading to the formation of nanoribbon. Such amorphous silicon nanoribbon is used for the fabrication of resistor

Silicon nanowires synthesis for chemical sensor applications

WOSInternational audienceSilicon nanowires (SiNWs) are synthesized following two methods: i) the VLS (Vapor-Liquid-Solid) growth technique (bottom up approach), and ii) the sidewall spacer fabrication (top down approach) commonly used in microelectronic industry. The VLS growth technique uses gold nanoparticles to activate the vapor deposition of the precursor gas and initiate a 100 nm diameter SiNWs network growth. In the case of the sidewall spacer method, a polysilicon layer is deposited by LPCVD (Low Pressure Chemical Vapor Deposition) technique on SiO2 wall patterned by conventional UV lithography technique. Polysilicon film is then plasma etched. Accurate control of the etching rate leads to the formation of spacers with a 100 nm curvature radius that can be used as polysilicon NWs. Each kind of nanowires is integrated into resistors fabrication. Electrical measurements show the potential usefulness of these SiNWs as chemical sensors

Growth-in-place deployment of in-plane silicon nanowires

International audienceUp-scaling silicon nanowire (SiNW)-based functionalities requires a reliable strategy to precisely position and integrate individual nanowires. We here propose an all-in-situ approach to fabricate self-positioned/aligned SiNW, via an in-plane solid-liquid-solid growth mode. Prototype field effect transistors, fabricated out of in-plane SiNWs using a simple bottom-gate configuration, demonstrate a hole mobility of 228 cm2/V s and on/off ratio >103. Further insight into the intrinsic doping and structural properties of these structures was obtained by laser-assisted 3 dimensional atom probe tomography and high resolution transmission electron microscopy characterizations. The results could provide a solid basis to deploy the SiNW functionalities in a cost-effective way

Perovskite based solar cells fabricated in air and nitrogen ambients

National audienc

Improvement of a Vertical Thin Film Transistor Based on Low-Temperature Polycrystalline Silicon Technology by Introduction of an Oxide Barrier between Drain and Source Layers

International audienc

Vertical Channel Thin Film Transistor: Improvement approach similar to multigate monolithic CMOS Technology

International audienc

Decreasing the off-current for vertical TFT by using an insulating layer between source and drain

International audienc

P-type and N-type multi-gate polycrystalline silicon vertical thin film transistors based on low-temperature technology

International audienceP-type and N-type multi-gate vertical thin film transistors (vertical TFTs) have been fabricated, adopting the low-temperature (T ⩽ 600 °C) polycrystalline silicon (polysilicon) technology. Stacked heavily-doped polysilicon source and drain are electrically isolated by an insulating barrier. Multi-teeth configuration is defined by reactive ion etching leading to sidewalls formation on which undoped polysilicon active layer is deposited. All the polysilicon layers are deposited from low pressure chemical vapor deposition (LPCVD) technique. Vertical TFTs are designed with multi gates, in order to have a higher equivalent channel width. Different active layer thicknesses have been attempted, and an ION/IOFF ratio slightly higher than 105 is obtained. P-type and N-type vertical TFTs have shown symmetric electrical characteristics. Different geometrical parameters have been chosen. IOFF is proportional to the single channel width, and to the tooth number. ION is only proportional to the tooth number. These devices open the way of a CMOS-like technology

Improvement in the determination by 1/f noise measurements of the interface state distribution in polysilicon TFTs in relation with the compensation law of Meyer Neldel

International audienceLow-frequency (1/f ) noise is studied in N-channel furnace solid phase crystallized (FSPC) and in laser solid phase crystallized (LSPC) polysilicon TFTs biased from weak to strong inversion. Noise analysis is supported by the theory of charge carrier trapping/detrapping at the interface tunnelling into gate oxide traps. The distribution of interface trap states (NT) is deduced from the number of carriers trapped into the oxide. Noise measurements for devices biased from weak to moderate inversion allow the determination of the distribution of deep level trap states associated with dangling bonds type defects (NTdb); whereas measurements from moderate to strong inversion give the distribution of shallow level trap states (NTts) associated with strained bonds defects. The noise analysis clearly shows that the slope of both exponential distributions equals to the reverse of the Meyer Neldel energy EMN (0.035 eV and 0.055eV for FSPC and LSPC TFT respectively). For LSPC devices the resulting distribution of interface states (NT=NTdb+NTts) is one decade lower and it is attributed to the effects of the laser annealing on the active layer crystal quality

Magnetic sensors with polysilicon TFTs

oral presentationInternational audienc