Modeling and enhanced control of hybrid full bridge–half bridge MMCs for HVDC grid studies

Modular multilevel converters (MMCs) are expected to play an important role in future high voltage direct current (HVDC) grids. Moreover, advanced MMC topologies may include various submodule (SM) types. In this sense, the modeling of MMCs is paramount for HVDC grid studies. Detailed models of MMCs are cumbersome for electromagnetic transient (EMT) programs due to the high number of components and large simulation times. For this reason, simplified models that reduce the computation times while reproducing the dynamics of the MMCs are needed. However, up to now, the models already developed do not consider hybrid MMCs, which consist of different types of SMs. In this paper, a procedure to simulate MMCs having different SM topologies is proposed. First, the structure of hybrid MMCs and the modeling method is presented. Next, an enhanced procedure to compute the number of SMs to be inserted that takes into account the different behavior of full-bridge SMs (FB-SMs) and half-bridge submodules (HB-SMs) is proposed in order to improve the steady-state and dynamic response of hybrid MMCs. Finally, the MMC model and its control are validated by means of detailed PSCAD simulations for both steady-state and transients conditions (AC and DC faults)

Modular Multi-level Converter Hardware-in-the-Loop Simulation on low-cost System-on-Chip devices

Comunicació presentada a IECON 2018 - 44th Annual Conference of the IEEE Industrial Electronics Society (October 21-23, 2018 Washington D.C., USA.)System-on-Chip (SoC) devices combine powerful general purpose processors, a Field-Programmable Gate Array (FPGA) and other peripherals which make them very convenient for Hardware-in-the-Loop (HIL) simulation. One of the limitations of these devices is that control engineers are not particularly familiarized with FPGA programming, which need extensive expertise in order to code these highly sophisticated algorithms using Hardware Description Languages (HDL). Notwithstanding, there exist High-Level Synthesis (HLS) tools which allow to program these devices using more generic programming languages such as C, C++ and SystemC. This paper evaluates SoC devices to implement a Modular Multi-Level Converter (MMC) model using HLS tools for being implemented in the FPGA fabric in order to perform HIL verification of control algorithms in a single low-cost device

Sizing and Short-Circuit Capability of a Transformerless HVDC DC-DC Converter

This work aims at optimizing the converter design of the double-T MMC DC-DC converter in terms of transmitted power per submodule and also in terms of transmitted power per silicon area, while, at the same time, providing the capability to block dc faults. Firstly, the converter operation is described and the optimal values of the inner ac and dc voltages that minimize device power rating are derived. Next, the submodule topology is analyzed and a thorough study on the converter capability for blocking fault currents is carried out, showing that the converter is able to isolate dc faults both at the input and at the output of the converter. Finally, the previous analytical study is verified by means of detailed PSCAD simulations

Protection Strategies for the Connection of Diode Rectifier-Based Wind Power Plants to HVdc Interconnectors

The connection of diode rectifier (DR)-based wind power plants (WPPs) to existing or planned high-voltage dc (HVdc) interconnectors can lead to important savings on cost and system robustness. Since the DR station usually operates in a bipolar configuration, its connection to symmetric monopoles is particularly challenging. However, there are no published detailed studies on the protection of DR connection WPPs to symmetric monopole interconnectors or even to bipolar interconnectors. This article includes the comparative study of five different protection strategies for such systems, including both solid and resistive DR station grounding and strategies with and without the use of dc-circuit breakers (dcCBs). An analytical study allows for the calculation of fault current during fault onset for both half-bridge and hybrid modular multilevel converter (MMC) stations. Using detailed electromagnetic transient (EMT) simulation studies, the different protection strategies are evaluated in terms of current, voltage, and isolation requirements of each element, as well as the need for dcCBs, fast communication, or larger surge arresters. Moreover, a distance fault detection algorithm is included for the wind turbine converters to distinguish between local ac-grid and dc-cable faults. From the simulation results, it is possible to conclude that DR high-impedance grounding, together with wind turbine distance protection, can be used for the protection of DR-based offshore WPPs connected to symmetric monopole interconnectors without requiring dcCBs

Analysis of the Performance of MMC Under Fault Conditions in HVDC-Based Offshore Wind Farms

This paper analyzes the behavior of a modular multilevel converter-high-voltage direct-current (MMC-HVDC)-connected offshore wind power plant (WPP) during dc faults. For that purpose, detailed models of the dc cable, MMC stations, and transformers have been used in order to obtain reliable results. The influence of the WPP control method in the short-circuit behavior of the HVDC link has also been studied. Results show that the dynamics of the WPP contribution to pole-to-ground faults are slightly slower than those of the wind turbines current control loops. Therefore, the wind turbine front-end converters can be used to reduce the peak and average value of the fault current in such a system. Moreover, it has been found that ferroresonant oscillations can appear in the offshore ac grid when the WPP delivers constant power during faults.This work was supported in part by the Spanish Ministry of Economy funds under Grant DPI2014-53245-R, in part by Universitat Jaume I under Grants P1·1B2013-51 and E-2014-24, and in part by CONICYT/FONDAP/15110019 and Fondecyt/1151325. Paper no. TPWRD-01518-2014

Integrated control of offshore wind farms and HVDC links with MML converters

This thesis analyzes the integration of large quantities of offshore wind power into power systems through point-to-point or multiterminal HVdc grids that use modular multilevel converters (MMC). Firstly, a simplified method to simulate MMCs is developed with the objective of reducing the simulation times. Secondly, a new control strategy for offshore wind power plants connected through MMC-HVDC links is developed in order to meet the requirements of the new ENTSO-E grid codes (for instance, island operation or black-start). Next, a mathematical study is carried out to estimate the values of the DC fault currents in HVDC grids and the response of several wind power plant control strategies are analyzed in the event of DC faults. Finally, a new DC-DC MMC topology is proposed for HVDC grids.En la tesis se analiza la integración de grandes cantidades de energía eólica en los sistemas eléctricos de potencia a través de redes HVDC punto a punto y multipunto que usan convertidores modulares multinivel (MMC). En primer lugar se desarrolla un modelo que permite reducir los tiempos de simulación a la hora de modelar los MMCs. A continuación se propone una nueva estrategia de control para parques eólicos marinos que permita cumplir con los nuevos requisitos exigidos en los nuevos códigos de red desarrollados por ENTSO-E (por ejemplo, funcionamiento en isla o arranque sin fuentes de energía externas). A continuación se desarrolla un modelo teórico para el estudio de las corrientes de cortocircuitos en redes HVDC y se analiza la respuesta de distintos tipos de controles de parques eólicos ante cortocircuitos en la red DC. Finalmente se propone una nueva topología de convertidor DC-DC MMC para redes HVDC

Multivariable phase-locked loop free strategy for power control of grid-connected voltage source converters

A multivariable control strategy in a reference frame for grid-connected voltage source converters (VSCs) without using a phase-locked loop (PLL) is presented in this paper. First, common VSC controls such as vector current control (VCC) and grid voltage modulated direct power control (GVM-DPC) are analyzed and their main drawbacks are identified. Then, the multivariable control strategy is presented, including the implementation of saturation and anti-windup mechanisms, and limitation of overcurrents. Next, different uncertainty channels that may lead to instability in each approach are analyzed, showing the drawbacks related to the use of a PLL, which are avoided in our proposal. The effectiveness of the three strategies is compared by means of MATLAB/Simulink simulations, showing that the proposal presents a more robust behavior, specially in weak grids.Funding for open access charge: CRUE-Universitat Jaume

Embedded Real-Time Simulator for Sensorless Control of Modular Multi-Level Converters

This paper suggests the application of an embedded real-time simulator (eRTS) in the context of voltage–sensorless control of a modular multilevel power converter (MMC). This eRTS acts as an observer and ensures digital redundancy in the case of any fault occurring among the capacitor voltage sensors of the MMC submodules. Hence, in such a faulty situation, the MMC controller switches from the measured voltages to their estimated counterparts. As for the digital implementation, to ensure a high level of integration of the overall control system, the Xilinx Zynq7020 system-on-chip field programmable gate array (SoC-FPGA) device was used. The controller was implemented in the hardwired ARM Cortex-A9 processor, with a 100 µs time step. Regarding the time-sensitive blocks (PWM, eRTS and measurements filtering), a full hardware implementation was privileged, using the FPGA fabric. The execution time of these blocks was 710 ns with a 100 MHz system clock, and the synchronization with the analog to digital acquisition chain was made with a 5 µs time resolution. The whole proof-of-concept system was experimentally tested, including the time/area evaluation of the implemented designs and the experimental validation of the eRTS estimations in both healthy and faulty scenarios