A memory reliability enhancement technique for multi bit upsets

International audienceTechnological advances allow the production of increasingly complex electronic systems. Nevertheless, technology and voltage scaling increased dramatically the susceptibility of new devices not only to Single Bit Upsets (SBU), but also to Multiple Bit Upsets (MBU). In safety critical applications, it is mandatory to provide fault-tolerant systems, providing high reliability while meeting applications requirements. The problem of reliability is particularly expressed within the memory which represents more than 80 % of systems on chips. To tackle this problem we propose a new memory reliability techniques referred to as DPSR: Double Parity Single Redundancy. DPSR is designed to enhance computing systems resilience to SBU and MBU. Based on a thorough fault injection experiments, DPSR shows promising results; It detects and corrects more than 99.6 % of encountered MBU and has an average time overhead of less than 3 %

A Fault Injection Platform for Early-Stage Reliability Assessment

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A Comprehensive Fault Injection Strategy for Embedded Systems Reliability Assessment

International audienceThe embedded systems industry is moving towards the integration of higher performance, yet less reliable electronic components into new product generations. Technology and voltage scaling increased dramatically the susceptibility of new devices not only to Single Bit Upsets (SBU), but also to Multiple Bit Upsets (MBU). However, the system reliability assessment at the design phase of fault-tolerant computer systems is a complex and critical task. In this context, it is mandatory to enhance reliability analysis and evaluation techniques at early-stage of the system development. In this paper, we present a technique for reliability evaluation of embedded systems at early-stage by taking into account the application behavior and SBU/MBU phenomena. Instead of using the random fault injection, our approach models the architecture behavior under real working conditions. Our results demonstrate the efficiency of the proposed fault injection simulation platform for early-stage reliability studies

Designing Drone Systems with Papyrus for Robotics

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Enhanced quality using intensive test and analysis on simulators

Conference of 18th Euromicro Conference on Digital System Design, DSD 2015 ; Conference Date: 26 August 2015 Through 28 August 2015; Conference Code:117072International audienceEmbedded systems are becoming ubiquitous and are subject to demanding standards in both safety and reliability. Modern vehicles, which must respect ISO 26262 standards, use up to 100 Electronic Control Unit (ECUs). Advances in microelectronics enable integration of more functions in the ECU, but at the cost of greater unreliability in hostile operating environments, such as electromagnetic fields, temperature, and humidity. Their software mainly drives embedded system flexibility and smartness. However due to lack of automation, its validation and verification (V&V) takes place throughout the design process and tends to swallow up 40% to 50% of the total development cost. The 'Enhanced Quality Using Intensive Test Analysis on Simulators' (EQUITAS) project intends to limit the impact of software V&V on embedded systems cost and time-To-market while improving reliability and functional safety. Project activities include: development of a continuous tool-chain to automate the V&V process of embedded computers, improving the relevance of the test campaigns by detecting the redundant tests using equivalence classes, providing assistance for hardware failure effect analysis (FMEA), and finally assessing the tool-chain under the ISO 26262 requirements

EQUITAS: A tool-chain for functional safety and reliability improvement in automotive systems

International audienceTo support advanced features such as hybrid engine control, intelligent energy management, and advanced driver assistance systems, automotive embedded systems must use advanced technologies. As a result, systems are becoming distributed and include dozens of Electronic Control Units (ECU). On the one hand, this tendency raises the issue of robustness and reliability, due to the increase in the error ratio with the integration level and the clock frequency. On the other hand, due to a lack of automation, software Validation and Verification (V&V) tends to swallow up 40% to 50% of the total development cost. The ``Enhanced Quality Using Intensive Test Analysis on Simulators'' (EQUITAS1) project aims (1) to improve reliability and functional safety and (2) to limit the impact of software V&V on embedded systems costs and time-to-market. These two achievements are obtained by (1) developing a continuous tool-chain to automate the V&V process, (2) improving the relevance of the test campaigns by detecting redundant tests using equivalence classes, (3) providing assistance for hardware failure effect analysis (FMEA) and finally (4) assessing the tool-chain under the ISO 26262 requirements