Capacity Results on Multiple-Input Single-Output Wireless Optical Channels

This paper derives upper and lower bounds on the capacity of the multiple-input single-output free-space optical intensity channel with signal-independent additive Gaussian noise subject to both an average-intensity and a peak-intensity constraint. In the limit where the signal-to-noise ratio (SNR) tends to infinity, the asymptotic capacity is specified, while in the limit where the SNR tends to zero, the exact slope of the capacity is also given.Comment: Submitted to IEEE Transactions on Information Theor

SynZEN: a hybrid TTA/VLIW architecture with a distributed register file

The quest for higher performance within a certain power budget in the fields of embedded computing demands unconventional architectural approaches. To this end, in this paper we present synZEN (sZ): a (micro-)architecture that combines features of very long instruction word (VLIW) and transport triggered architectures (TTAs) to cover the needs of different applications. SynZEN features a distributed register file (RF) (i.e., each functional unit (FU) has its own RF) and a wide memory connection to exploit spatial data locality. FPGA synthesis results demonstrate that due to the distributed RF the sZ design can be implemented in less area (in terms of FPGA slices) than existing TTA and VLIW designs. Furthermore, using two micro-benchmarks we show that because of the wide memory connection, sZ outperforms both the TTA as well as the VLIW design

A hybrid transport/control operation triggered architecture

We present an approach to a scalable and extensible processor architecture with inherent parallelism named synZEN. One aim was to create a synthesizable application specific processor which can be mapped to an FPGA. Besides architectural features like the interconnection network for flexible data transport and synZEN units with communication managing interface we give an overview of the programming model, show basic operation design and depict assembler notations to program these architecture. The paper closes with a brief toolchain overview and some synthesis results that support our design decisions