3D Architecture and Replaceable Layers for Label-Free DNA Biochips

Recent advances in bio-sensing technologies have led to design of bio-sensor arrays for rapid identification and quantification of various biological agents such as drugs, gene expressions, proteins, cholesterol, fats, etc. Various dedicated sensing arrays are already available commercially to monitor some of these compounds in a sample. However, monitoring the simultaneous presence of multiple agents in a sample is still a challenging task. Multiple agents may often attach to the same probes on an array which makes it difficult to design a chip that can distinguish such agents (leading to low specificity). Thus, sophisticated algorithms for targets identification need to be implemented in biochip in order to maximize the number of distinguishable targets in the samples. The proposed algorithms are also required to introduce sophisticated signal processing and more intelligence on-chip. Dealing with these new processing and information technology demands constraints also require more innovative approaches towards hybrid integration technologies. To address such new demands, we discuss in this paper an innovative 3D-integrated bio-chips especially dedicated to label-free DNA detection

Power-gated MOS current mode logic (PG-MCML): a power aware DPA-resistant standard cell library

MOS Current Mode Logic (MCML) is one of the most promising logic style to counteract power analysis attacks. Unfortunately, the static power consumption of MCML standard cells is significantly higher compared to equivalent functions implemented using static CMOS logic. As a result, the use of such a logic style is very limited in portable devices. Paradoxically, these devices are the most sensitive to physical attacks, thus the ones which would benefit more from the adoption of MCML

Validation of the porous-medium approach to model interlayer-cooled 3D-chip stacks

Interlayer cooling is the only heat removal concept which scales with the number of active tiers in a vertically integrated chip stack. In this work, we numerically and experimentally characterize the performance of a three tier chip stack with a footprint of 1cm2. The implementation of 100μm pitch area array interconnect compatible heat transfer structures results in a maximal junction temperature increase of 54.7K at 1bar pressure drop with water as coolant for 250W/cm2 hot-spot and 50W/cm2 background heat flux. The total power removed was 390W which corresponds to a 3.9kW/cm3 volumetric heat flow. An efficient multi-scale modeling approach is proposed to predict the temperature response in the complete chip stack. The experimental validation confirmed an accuracy of +/- 10%. Detailed sub-domain modeling with parameter extraction is the base for the system level porous-media calculations with thermal field-coupling between solid – fluid and solid – solid interfaces. Furthermore, the strength and weakness of microchannel and pin fin heat transfer geometries in 2-port and 4-port fluid architectures is identified. Microchannels efficiently mitigate hot spots by distributing the dissipated heat to multiple cavities due to their low porosity. Pin fins with improved permeability and convective heat dissipation are advantageous at small power map contrast and aligned hot spots on the different tiers. Large stacks of 4cm2 can be cooled sufficiently by the 4-port fluid delivery architecture. The flow rate is improved four times compared to the 2-port fluid manifold. The non-uniformity of the flow in case of the 4-port demands a more careful floor- planning with hot spots placed in the chip stack corners. This is especially true in case of communicating heat transfer geometries such as pin fin structures with zero fluid velocity in the stack center. This large velocity contrast can be reduced by the implementation of non- communicating microchannels