Hanay, M. S.

Hatirnaz, I.

Kalkan, O.

Leblebici, Y.

Infoscience - École polytechnique fédérale de Lausanne

Multi-Chip Implementation of a High-Speed Sorting Engine Based onRank-Ordering¨O.Kalkan M.S. Hanay ˙I. Hatırnaz and Y. LeblebiciSabancı University California Institute of Technology Swiss Federal Institute of Technology(EPFL)Graduate School Pasadena, CA Microelectronic Systems Laboratory (LSM)Kocaeli, Turkey 91125 USA Lausanne, CH-1015, Switzerlandozlem@su.sabanciuniv.edu selim@its.caltech.edu {ilhan.hatirnaz,yusuf.leblebici}@epfl.chAbstract— A multi-chip-module (MCM) implementation of abinary sorting engine is presented. Previously, a bit-serial sorterarchitecture was proposed, which is able to sort up to 63 16-bitnumbers in 78 clock cycles, which includes the time spent for theserial data input. This architecture was put on silicon, using a con-ventional 0.35µm technology, resulting in an area of 13 mm2 andan operation at a clock frequency of approximately 200 MHz. Theproposed sorting engine consists of individual sorter units and acontrol block, which takes care of the data transfer between theseunits.I. INTRODUCTIONThe task of sorting is an expensive operation in terms of area-time complexity; software-based solutions require word-levelsorting and can become computationally intensive. The overallcomplexity of hardware-based solutions usually increases veryrapidly with the size of the input vector set and with the bit-length of the input vectors.In this paper, the implementation of a parallel sorting engineis proposed. This sorting engine is built using individual localsorters, which are able to process up to 127 vectors at a time. Acontrol logic is developed to synchronize the local sorters andprovide safe data-exchange among individual sorters, which isdictated by the parallel sorting algorithm described below.A summary of the previous work on the local sorting engineand the algorithm used in realizing the parallel sorting engineare given in Section II. The following two sections, SectionIII. and IV. talk about the proposed system architecture and itshardware realization.II. SORTING ALGORITHMA. Previous Work & BackgroundThe main building block of the proposed parallel sorting ar-chitecture is rank-ordering based sorter block [1] [2], for which,a bit-serial algorithm was chosen as the basis [3].The overall architecture of the sorting engine is shown in Fig-ure 1. The flow of data through the modular sorter core is beingregulated by complementary input and output shift register ar-rays, which are used to stagger indidivual bit-planes of eachinput vector to enable bit-level pipelined operation. The con-trol logic is responsible for regulating the data circulation path,and for applying the rank selection signals to the individual bit-planes, in ascending or descending order. The fact that eachindividual bit-plane is capable of processing a different rankat any given time significantly increases the overall efficiencyof this architecture. In a typical sorting run, the control logicsimply requests each bit-plane to process a different rank ineach clock cycle, either beginning from the maximum rank anddescending, or beginning from the minimum rank and ascend-ing. It was demonstrated that this sorting engine is capable ofproducing a fully-sorted output vector set in any rank order in(m+n-1) clock cycles, i.e., in linear time, where, ’m’ is the num-ber of vectors to be sorted and ’n’ is the bit-length, the numberof bits used to represent each input vector.INPUTSHIFTREGISTERARRAYused to obtaindata vectors.bit−wise staggeredused to convert bit−wisestaggered output vectorsback to normal.CONTROLBLOCKControl feedbackto the userfrom the userto the majority gatesControl signalsRank control bussorter datainput busOUTPUTSHIFTREGISTERARRAYsorter dataoutput busDataMUXcontrol busSORTER CORESorter slice − MSBSorter slice − MSB2Sorter slice − MSB3Sorter slice − LSBFig. 1. Top-level blocks in the sorter architecture. This block is one of the mainbuilding blocks of the proposed parallel sorting architecture.The bit-serial operation of the algorithm suggests a sim-ple bit-level pipelined data architecture, consisting of datamodifier-propagator block (ROF cells) to handle fine-graineddata selection, and the majority decision blocks (majority func-tion) to determine the output bits. The modular two dimen-sional array architecture consisting of these two major blocksenables fully scalable construction of structures of arbitrarywindow size and bit-length. The bit-lenght dictates the numberof majority decision gates (rows or slices), whereas the windowsize determines the number of ROF cells driving one of thesemajority gates in one slice (columns). The structure of one rowis shown in Figure 2.The programmable majority function is the key operation thatmust be performed in each row. This function also determinesthe overall operation speed (i.e., the clock frequency), sincethe m-input majority function must be performed in each clockcycle. The majority gate has been realized with fully combina-tional parallel counter, which consists of full adders connectedin a tree network and an output comparator.A sorting engine based on the architecture described abovefor processing 127 input vectors of 16-bits has been realizedusing conventional 0.35µm technology. The architecture con-sists of 16 rows, where each row is capable of processing 127bits simultaneously. This 127x16 sorting engine is the mainbuilding block of the proposed larger parallel-sorting architec-ture.QDDFFSelect signalfrom thecontrol blockshift registersfrom the inputShifted dataPropagating datafrom the bit-sliceSelect signalfor the nextlower bit-sliceto the bit-sliceShifted datamajority gateInput bus to thethrough the ROF CellsActual input data flowGATEMAJORITYActual Data output ofthe last ROF CellRANKREGRank busfrom thecontrol blockBit-slice outputshift registerto the outputmajority gateOutput of the(fed back to the ROF Cells)Rank for thebit-slicenext lowerBAYMUXSCELLROFCELLROFROFCELLFig. 2. The block-level structure and the signal flow in one sorter bit-slice.B. Neighborhood-Sort AlgorithmTo be able to process larger numbers of input vectors, thereis a need for an algorithm, which would make smaller sorterblocks run in parallel and provide that a large number of inputvectors are sorted either in ascending or in descending order.Among different parallel sorting algorithms, the neighborhoodsort algorithm is chosen for its simplicity and its applicabilityin the forementioned sorting architecture [4]. Figure 3 showsan example for how the algorithm works. In this example, thegoal is to sort 12 integers (from 1 to 12), which are given ina random order, using three sorting blocks, each of which, iscapable of sorting up to four numbers in one step. The al-gorithm is mainly a loop of individual sorting of the data ineach sorter block, transferring the highest “k” numbers (k =2 inthe given example) to the neighboring block (the block at theright), do individual sorting again with the new block contentsand then providing the “k” smallest numbers to the neighbor atthe opposite side (the block at the left side), until the sorting iscompleted. This loop dictates that there has to be a check stepafter every individual sorting of each block contents to see ifthe numbers are already in the desired order (min-to-max in theexample).In the example, each sorter first sorts its contents and thentransfer the two largest numbers to the neighboring sorter block(at the right side). The right-most block stores its two largestnumbers for a later step, which are not taken into account justfor this one step; and it gets another two numbers from theneighboring block to its left. After the next sort operation,this time each sorter block sends its two smallest number toits neighbor at its left. Also, the two numbers stored by theright-most block are shifted inside that block and the sorting isrepeated again for each sorter block. This operation goes onuntil all the numbers are sorted in the increasing order startingfrom left going to right. As one can easily observe from Figure3, to sort eight numbers in increasing order with three individ-ual sorter blocks, took four sorting and four shifting operations.Fig. 3. The operation of the neighborhood-sort algorithm.Fig. 4. The implementation of the slightly-changed neighborhood-sort algo-rithm as part of the proposed sorting architecture.The proposed architecture employs a slightly changed versionof this algorithm, where, “k” possible smallest numbers (“0 0”)are fed from the left side (where we assume that the sorter blockprocessing the minimum numbers is located) and “k” highestpossible numbers (represented with “F F”) are provided fromthe right side (at which, we assume the sorter block that at theend of the process will store the highest numbers, is located),as seen in Figure 4. Whenever Sorter1 needs to transfer datafrom Sorter2, its two ’0’s are thrown away, later when the datais shifted right, Sorter1 recovers the zeros back. This changein the algorithm makes all the sorting blocks act the same wayindependent of their location and therefore eases the the job ofthe control logic.III. SYSTEM ARCHITECTUREThe modified neighborhood-sort algorithm dictates the needfor two main operations:• Transfer of data from one sorter block to other.• Sorting of the content of each sorter block.The previous section presented a sorter block, which can han-dle up to 127 16-bit input vectors. This block is used for im-plementing each ’Sorter’ cell of the table shown in Figure 4.Hence, each cell of the table corresponds to a sorter module of127 input vectors at the implementation side.The other main operation listed above, the transfer of dataamong blocks, requires a data storage structure and a dedicatedcontrol system to ensure the transferred data is received by thecorrect sorter module. The implementation of the data trans-fer is illustrated in Figure 5. It is shown that the sorter blockreceives half of its input vectors from one of its neighboringblocks, either from the left one or from the right depending onthe type of data being transferred, and the other half consists ofthe vectors which were sorted during the previous step by theblock itself. At the same time, each sorter module sends corre-Communication Control outputCONTROLFILEREGISTERCOMMUNICATIONCONTROLLERData SelectionMultiplexersData toneighborsControlinputsSORTERCOREISRAOSRAData from leftData from rightOwn dataSORTERFig. 5. Implementation of the data transfer among neighboring sorter blocks. ISRA and OSRA stand for Input and Output Shift Register Array, respectively.sponding half of its sorted content to its neighbors, which willbe accepted only by the appropriate sorter module.Assuming desired sorting order is from minimum to maxi-mum, i.e., the maximum vector appears first at the output ofevery sorter module, the corresponding data flow is given be-low in Table I, including the number of clock cycles requiredfor each operation. It should be noted that the net effect ofsuch a scheme is to push the larger vectors to the rightmostsorter modules and the smaller vectors to the leftmost sortermodules, until the sorting operation is accomplished globally,which is checked by the “Global check” routine. It can be seenthat the system operates in units of 143 clock cycles, which isdetermined by the total number of registers that a input vec-tor must be shifted through; 127 for storing the results of thesorting operation, plus, 16 to hold them inside the correspond-ing block during the global check. One complete round takes4× 143 = 572 clock cycles, after which, another round starts.The so-called “global check” step is used to check if at anymoment all the vectors are sorted in the desired order. Underthe assumption that a sorting system has ’n’ sorter modules, thecondition to confirm the finish of the global sorting operation isthe synchronous correctness of all the local conditions below:min (Sorter #1) > max (Sorter #2)min (Sorter #2) > max (Sorter #3)· · · · · ·min (Sorter #(n − 1)) > max (Sorter #n)IV. HARDWARE REALIZATIONThe generic 127 x 16-bit sorter core has been synthesized,and mapped on a 0.35 um CMOS standard cell library includ-ing the register blocks, and the control-communication circuits.The structure consists of 16 individual rows (see Figure 1), eachcorresponding to one bit-slice. Each row contains 127 ROFcells that are responsible for the low-level implementation ofthe bit-serial sorting algorithm. The critical path was identifiedas the 127-bit majority decision circuit that needs to operate foreach bit slice concurrently. It was found that the worst case in-put to output delay of this 127-bit majority decision block canTABLE IREGULAR OPERATION OF THE SYSTEM.NOTE THAT THE VALUES FOR CLOCK CYCLES ARE VALID ONLYFOR THE CASE, WHERE THE SYSTEM EMPLOYS SORTER MODULESOF 127 VECTORS.# of clock Operation Operationcycles in registers in sorters0-63 Shift in data Produce thefrom left maximum half64-127 Shift in own data Produce theminimum half127-143 Shift data& Start filling ISRAGlobal check143-286 null Shift datainside core286-349 Shift in own data Produce max half349-413 Shift in data Produce thefrom right minimum half413-429 Shift data& Start filling ISRAGlobal check429-572 null Shift datainside corebe optimized by using the procedural description of the ma-jority function. This results in a worst case delay of approxi-mately10 ns for the majority block, allowing a clock frequencyof 100 MHz for the overall system.The standard cell realization of one sorter core block is shownin Figure 6 after placement and routing using Silicon Ensem-ble. The dimensions of the block are 845µm x 820µm, in-cluding the register files and the local control unit. Once thebasic building block of the system is generated, a much larger-capacity parallel sorting engine can be constructed by linkinga number of such units in cascade configuration, as depictedin Figure 7 for 16 individual units. The key point is that thecapacity of the system can be arbitrarily increased by simply at-taching additional units, limited only by the clock distributionnetwork and the data transmission speed between the modules.To achieve a cost-effective solution, it was decided to place 4individual sorter units on each chip, which results is a relativelysmall chip size (using 0.35 um CMOS technology) of approxi-mately 25mm2 including the I/O pads. To reduce the cost evenFig. 6. Standard-cell layout view of the 127x16 sorting engine.Fig. 7. The top-level placement of the sorter modules and the direction of thedata path.more, only a single layer of conductor is used in MCM andmuch effort is spent on ensuring that there isn’t any overlap-ping paths. Utilizing 16 such chips in a cascade configurationproduces an aggregate sorting capacity of 8k x 16-bit (= 128kbits). This capability is significantly higher than those of pre-viously reported sorting arrangements [5], [6].The control circuitry of the sorter is designed in a way, whichmakes it possible to send data to the MCM sorter and to receivedata from it. This communication can be realized by connect-ing the sorter to a serial port and writing an assembly code totake care of the communication.V. CONCLUSIONSA multi-chip implementation of parallel sorting engine is pre-sented. The proposed architecture is based on parallel process-ing of a large number input vectors by a number of individualsorting engines, which exchange data after finishing the localsorting operation. The design given in this paper has a capacityof sorting 8k input vectors, each of which is 16 bits.ACKNOWLEDGMENTThe authors thank Ms. Tug˜ba Demirci of Cypress Semicon-ductors Istanbul Design Center, for her invaluable contributionsin the early stages of this research.REFERENCES[1] ˙I. Hatırnaz, Y. Leblebici, “Scalable Binary Sorting Architecture Based onRank-Ordering”, Proceedings of ISPACS 2000, Hawaii, October 2000.[2] T. Demirci, ˙I. Hatırnaz, Y. Leblebici, “CMOS Realization of a ScalableHigh-Performance Binary Sorting Engine Suitable for Embedded Appli-cations”, ASIC/SOC 2000, Rochester, NY, September 2002.[3] B.K. Kar, D.K. Pradhan, “ A New Algorithm for Order Statistic and Sort-ing”, IEEE Trans. on Signal Proc., vol. 41, pp 2688-2694, August 1993.[4] A. Park and K. Balasubramanian, “Improved Sorting Algorithms for Par-allel Computers,” Proceedings of 15th Annual Conference on ComputerScience, 1987, pp. 239-244.[5] W.K. Lam and C.K. Li, “Binary sorter by majority gate,” IEE ElectronicLetters, Vol. 32, July 1996.[6] C.C. Lin, C.J. Kuo, “Fast response 2-D rank order algorithm by usingmax-min sorting network,” International Conference on Image Process-ing 1996, Vol. 1, pp. 403-406.

Multi-Chip Implementation of a High-Speed Sorting Engine Based on Rank-Ordering

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