The Beetle Reference Manual - chip version 1.3, 1.4 and 1.5

This paper details the electrical specifications, operating conditions and port definitions of the readout chips Beetle 1.3, 1.4 and 1.5. The chip is developed for the LHCb experiment and fulfils the requirements of the silicon vertex detector (VELO, PUS), the silicon tracker and the RICH detectors in case of multi-anode photomultiplier readout. It integrates 128 channels with low-noise charge-sensitive preamplifiers and shapers. The pulse shape can be chosen such that it complies with LHCb specifications: a peaking time of 25 ns with a remainder of the peak voltage after 25 ns of less than 30%. A comparator per channel with configurable polarity provides a binary signal. Four adjacent comparator channels are being ORed and brought off chip via LVDS ports. Either the shaper or comparator output is sampled with the LHC bunch-crossing frequency of 40 MHz into an analogue pipeline. This ring buffer has a programmable latency of max. 160 sampling intervals and an integrated derandomising buffer of 16 stages. For analogue readout data is multiplexed with up to 40 MHz onto 1 or 4 ports. A binary readout mode operates at up to 80 MHz output rate on two ports. Current drivers bring the serialised data off chip. The chip can accept trigger rates up to 1.1 MHz to perform a dead-timeless readout within 900 ns per trigger. For t estab ility and calibration purposes, a charge injector with adjustable pulse height is implemented. The bias settings and various other parameters can b

The Beetle Reference Manual: chip version 1.2

This paper details the electrical specifications, operating conditions and port definitions of the readout chip Beetle 1.2. The chip is developed for the LHCb experiment and fulfils the requirements of the silicon vertex detector (VELO, VETO), the silicon tracker and the RICH detector in case of multi-anode photomultiplier readout. It integrates 128 channels with low-noise charge-sensitive preamplifiers and shapers. The pulse shape can be chosen such that it complies with LHCb specifications: a peaking time of 25 ns with a remainder of the peak voltage after 25 ns of less than 30%. A comparator per channel with configurable polarity provides a binary signal. Four adjacent comparator channels are being ORed and brought off chip via LVDS ports. Either the shaper or comparator output is sampled with the LHC-bunch-crossing frequency of 40 MHz into an analog pipeline. This ring buffer has a programmable latency of max. 160 sampling intervals and an integrated derandomising buffer of 16 stages. For analog readout data is multiplexed with up to 40 MHz onto 1 or 4 ports. A binary readout mode operates at up to 80 MHz output rate on two ports. Current drivers bring the serialised data off chip. The chip can accept trigger rates of up to 1.1 MHz to perform a dead-timeless readout within 900 ns per trigger. For te stabi lity and calibration purposes, a charge injector with adjustable pulse height is implemented. The bias settings and various other parameters can be controlled via a standard I2C-interface. Appropriate design measures have been taken to ensure the radiation hardness against total ionising dose effects in excess of 10 Mrad. A robustness against Single Event Upset is achieved by redundant logic

Compact Frontend-Electronics and Bidirectional 3.3 Gbps Optical Datalink for Fast Proportional Chamber Readout

The 9600 channels of the multi-wire proportional chamber of the H1 experiment at HERA have to be read out within 96 ns and made available to the trigger system. The tight spatial conditions at the rear end flange require a compact bidirectional readout electronics with minimal power consumption and dead material. A solution using 40 identical optical link modules, each transferring the trigger information with a physical rate of 4 x 832 Mbps via optical fibers, has been developed and commisioned. The analog pulses from the chamber can be monitored and the synchronization to the global HERA clock signal is ensured.Comment: 13 pages, 10 figure

AC-KBO Revisited

Equational theories that contain axioms expressing associativity and commutativity (AC) of certain operators are ubiquitous. Theorem proving methods in such theories rely on well-founded orders that are compatible with the AC axioms. In this paper we consider various definitions of AC-compatible Knuth-Bendix orders. The orders of Steinbach and of Korovin and Voronkov are revisited. The former is enhanced to a more powerful version, and we modify the latter to amend its lack of monotonicity on non-ground terms. We further present new complexity results. An extension reflecting the recent proposal of subterm coefficients in standard Knuth-Bendix orders is also given. The various orders are compared on problems in termination and completion.Comment: 31 pages, To appear in Theory and Practice of Logic Programming (TPLP) special issue for the 12th International Symposium on Functional and Logic Programming (FLOPS 2014