27 research outputs found

    Semantics of UML 2.2 State Machines in Rewriting Logic

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    While the semantics of (labeled) transition systems and the relations between these are well understood. However, the same has not yet been achieved for UML 2.2 state machines. Their many semantics often is defined in terms of labeled transition systems, because the standard document is ambiguous. A formal, modular core semantics for UML 2.2 state machines is given in rewriting logic

    Semantic Issues in UML 2.0 State Machines

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    A precise semantics for the modeling language UML 2.0 is necessary for code generation and for formal verification of models during the early stages of design. We present a formal semantics of the firing of transitions in UML 2.0 state machines. In particular, we handle shallow/deep history pseudostates, final states, join/fork pseudostates, entry/exit actions and the different kinds of transition. Furthermore, our semantics captures all orderings of actions in a run-to-completion step. We point out ambiguities and uncertainties in the UML 2.0 standard, especially in the meaning of history pseudostates and priority between transitions. We discuss different attempts in resolving these

    TTSS'11 - 5th International Workshop on Harnessing Theories for Tool Support in Software

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    The aim of the workshop is to bring together practitioners and researchers from academia, industry and government to present and discuss ideas about: • How to deal with the complexity of software projects by multi-view modeling and separation of concerns about the design of functionality, interaction, concurrency, scheduling, and nonfunctional requirements, and • How to ensure correctness and dependability of software by integrating formal methods and tools for modeling, design, verification and validation into design and development processes and environments. • Case studies and experience reports about harnessing static analysis tools such as model checking, theorem proving, testing, as well as runtime monitoring

    Efficient Key Management System for Large-scale Smart RFID Applications

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    Due to low-cost and its practical solution, the integration of RFID tag to the sensor node called smart RFID has become prominent solution in various fields including industrial applications. Nevertheless, the constrained nature of smart RFID system introduces tremendous security and privacy problem. One of them is the problem in key management system. Indeed, it is not feasible to recall all RFID tags in order to update their security properties (e.g. update their private keys). On the other hand, using common key management solution like standard TLS/SSL is too heavy-weight that can drain and overload the limited resources. Furthermore, most of existing solutions are highly susceptible to various threats reaching from privacy threats, physical attacks to various technics of Man-in-the-Middle attacks. This paper introduces novel key management system, tailored to the limited resources of smart RFID system. It proposes light-weight mutual authentication and identity protection to mitigate the existing threats

    On Message Specifications in OCL

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    The object constraint language (OCL) is the established language for specifying of properties of objects and object structures. Recently an extension of OCL has been proposed for the specification of messages sent between objects

    Inter-Object and Intra-Object Concurrency in Creol

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    In traditional object-oriented languages, method calls are synchronous: The thread of control is passed from the caller to the callee, blocking the caller until the call is finished. This suits tightly coupled systems but leads to unnecessary delays in distributed environments, where objects are dispersed geographically. Another problem shared by thread-based object-oriented languages is that control threads may interfere with each other when operating on the same object. Creol is a language for concurrent objects that addresses these issues through two novel language constructs: asynchronous method calls and explicit processor release points.
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