Scalable digital-to-RF processor for multi-standard and multi-band low power wireless transmitter in 5 GHz and 60 GHz

Le domaine de la recherche dans les multi-standards, les systèmes multi-bandes, architectures, et circuits a été un thème populaire. La perspective est d'avoir des dispositifs qui peuvent être adaptés, parfaitement, aux différents réseaux tout en offrant d'excellentes fonctionnalités sur les différents technologies d’accès radio. Les architectures de transmetteurs configurables ciblant les cas d'utilisation complémentaires des WiFi-WiGig ont été étudiés. Des approches novatrices basées sur des DAC FIR semi-numériques configurables à grande vitesse sont proposées. Les DAC de FIR nécessitent des filtres longs avec des coefficients de résolution élevés pour atteindre des niveaux d'atténuation de stopband satisfaisants aux exigences de bruit hors bande. Normalement, cela limite la vitesse et se traduit par une grande surface de silicium. Dans ce travail, les techniques de conception de circuits sont développées de sorte qu'un élément de circuit unitaire réalisant un coefficient d'une fonction de transfert peut être réutilisé dans la réalisation d’un coefficient d'une autre fonction de transfert. Une puce prototype de passe-haut FIR DAC qui peut être configuré pour le fonctionnement de l'IEEE 802.11ac et les standards IEEE 802.11ad a été mise en œuvre sur une technologie CMOS 28nm FDSOI de STMicroelectronics. Le test De cette puce a démontré la validité des architectures d'émetteur proposées. Le puce prototype peut traiter des signaux des bandes de base aussi larges que 63,63 MHz et 300 MHz à une fréquence d'horloge de 1,4 GHz avec une consommation de 103,07 mW dans le 802.11ac et 86,89 mW dans le mode 802.11ad.The vision of research into multi-standard and multi-band systems, architectures, and circuits has been to develop devices which can hope seamlessly from one network to the other while delivering excellent functionality in different radio access technologies.In this work, configurable transmitter architectures based on FIR DACs which target WiFi-WiGig complementary use cases have been studied. FIR DACs require long filters with high resolution coefficients to meet high out-of-band noise attenuation. Normally, this limits speed and results in large area. In this work, circuit techniques are developed so that a unit circuit element realizing a coefficient of one transfer function can be re-used in realizing a different-valued coefficient of another transfer function. The work also proposes topologies that exploit digital signal processing at advanced nodes to implement quadrature modulation while realizing up-conversion, digital-to-analog conversion and image and quantization filtering in one configurable FIR DAC block. A prototype high pass FIR DAC chip which can be configured for processing IEEE 802.11ac and IEEE 802.11ad signals was implemented in ST CMOS 28nm FDSOI technology. The test of this chip has demonstrated the validity of the proposed transmitter architectures. The prototype chip can process baseband signals as wide as 63.63 MHz and 300 MHz at a clock frequency of 1.4 GHz while consuming 103.07 mW in the 802.11ac and 86.89 mW in the 802.11ad modes

Design of Ultra-Low Power Wake-Up Receiver in 130nm CMOS Technology

Wireless Sensor Networks have found diverse applications from health to agriculture and industry. They have a potential to profound social changes, however, there are also some challenges that have to be addressed. One of the problems is the limited power source available to energize a sensor node. Longevity of a node is tied to its low power design. One of the areas where great power savings could be made is in nodal communication. Different schemes have been proposed targeting low power communication and short network latency. One of them is the introduction of ultra-low power wake-up receiver for monitoring the channel. Although it is a recent proposal, there has been many works published. In this thesis work, the focus is study and comparison of architectures for a wake-up receiver. As part of this study, an envelope detector based wake-up receiver is designed in 130nm CMOS Technology. It has been implemented in schematic and layout levels. It operates in the 2.4GHz ISM band and consumes a power consumption of 69µA at 1.2V supply voltage. A sensitivity of -52dBm is simulated while receiving 100kb/s OOK modulated wake-up signals.This is a master's thesis work by a communication electronics student in a German company called IMST GmbH

Design of a 4th-Order Feed-Forward-Compensated Operational Amplifier for Multi-GHz Sampling Frequency Continuous-Time Bandpass Sigma-Delta Modulators

International audienceThis work presents a 4 th-order multi-stage, multi-path, feed-forward-compensated operational amplifier in 65 nm CMOS technology. It is designed to meet the requirements of a continuous-time bandpass Σ∆ modulator with multi-GHz sampling frequency. The designed amplifier is modular with each stage implemented based on a unit differential amplifier block and it meets its targets with smart placement of poles and zeros. The amplifier is simulated under the loading condition of a single-amplifier resonator which is in turn part of a 6 th-order Σ∆ modulator. The unloaded amplifier reaches a unity-gain-frequency of 38.29 GHz and a DC gain of 58 dB. With a parallel load of 440 fF and 300 Ω, representing the maximum load, the op-amp, including common-mode and biasing circuits, consumes a total of 18.98 mA from a supply voltage of 1.2 V. It is unconditionally stable with a phase margin of 54 • and has gains of 35 dB and 23 dB at 1 GHz and 2 GHz respectively

First Results of PEPITES, A New Transparent Profiler Based on Secondary Electrons Emission for Charged Particle Beams

International audienceThe PEPITES project* consists of a brand new operational prototype of an ultra-thin, radiation-resistant profiler capable of continuous operation on mid-energy (O(100 MeV)) charged particle accelerators. Secondary electron emission (SEE) is used for the signal because it only requires a small amount of material (10 nm); very linear, it also offers good dynamics. The lateral beam profile is sampled using segmented electrodes, constructed by thin film methods. Gold strips, as thin as the electrical conductivity allows (~ 50 nm), are deposited on an insulating substrate as thin as possible. While crossing the gold, the beam ejects the electrons by SEE, the current thus formed in each strip allows the sampling. SEE was characterized at ARRONAX with 68 MeV proton beams and at medical energies at CPO**. Electrodes were subjected to doses of up to 10⁹ Gy without showing significant degradation. A demonstrator with dedicated electronics (CEA) is installed at ARRONAX and will be used routinely with proton beams of 17-68 MeV for intensities of 100fA to 100nA. An overview of the design and first measurements will be presented, and system performances will be assessed

Development of a Transparent Profiler Based on Secondary Electrons Emission for Charged Particle Beams

International audienceThe PEPITES project* aims at realizing an operational prototype of an ultra-thin, radiation-resistant profiler able to permanently operate on mid-energy (O(100 MeV)) charged particle accelerators. PEPITES uses secondary electron emission (SEE) for the signal because it requires only a minimal thickness of material (10 nm); very linear, it also offers a great dynamic. The lateral beam profile is sampled using segmented electrodes, constructed by thin film methods. Gold strips, as thin as the electrical conductivity allows (~ 50 nm), are deposited on an as thin as possible insulating substrate. When crossing the gold, the beam ejects the electrons by SEE, the current thus formed in each strip allows the sampling. The technique was validated at ARRONAX with 68 MeV proton beams for intensities from 100 fA to 10 nA. SEE is characterized up to 100 nA at ARRONAX and medical energies at CPO**. Electrodes were subjected to doses of up to 10⁹ Gy without showing significant degradation. A demonstrator with dedicated electronics (CEA) will be installed at ARRONAX and used routinely. The performances of the system and its behavior over time will thus be characterized