Compressively strained Ge trigate p-MOSFETs

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2012.Cataloged from PDF version of thesis.Includes bibliographical references (p. 71-74).State of the art MOSFET performance is limited by the electronic properties of the material that is being used, silicon (Si). In order to continue performance enhancements, different materials are being studied for the extension of Si CMOS. One of the materials of interest, particularly for p-MOSFETs, is Ge because it has very high intrinsic hole mobility. Further improvements in hole mobility can be achieved by straining the material. At the same time it is important to study strained Ge transport in device architectures such as trigate MOSFETs. These devices offer the potential for better scalability than planar MOSFETs via improved electrostatics. The investigation of hole mobility in strained Ge trigate ("nanowire") p- MOSFETs is the focus of this work. To study the effects of strain on Ge as a p-channel material, Strained Germanium Directly on Insulator (SGDOI) substrates were fabricated. The substrates were strained to ~2.4% using lattice mismatch which originates from the growth of Ge on a relaxed Si₀.₆Ge₀.₄ epitaxial layer. A biaxially strained SGDOI substrate was patterned to form Ge nanowires which were measured by Raman spectroscopy to investigate the strain relaxation from the free surface. Another SGDOI substrate was used for nanowire trigate p-MOSFET fabrication. The semiconductor layer structure for the devices consisted of 10 nm-thick strained-Ge with a 5 nm-thick strained-Si cap. On-chip biaxially strained MOSFETs were compared to asymmetrically strained Ge nanowire devices. Significantly improved mobilities (~2x) were observed for nanowire devices with a width of 49 nm compared to the on-chip biaxially strained Ge controls. These mobilities are ~15x over Si universal hole mobility. The impact of strain on the transport of holes in long channel devices is also studied as a function of nanowire width. Mobility decreased for narrower nanowire MOSFETs, likely associated with increased sidewall line edge roughness scattering in narrow lines.by Winston Chern.S.M

Antiferroelectric negative capacitance from a structural phase transition in zirconia

Crystalline materials with broken inversion symmetry can exhibit a spontaneous electric polarization, which originates from a microscopic electric dipole moment. Long-range polar or anti-polar order of such permanent dipoles gives rise to ferroelectricity or antiferroelectricity, respectively. However, the recently discovered antiferroelectrics of fluorite structure (HfO$_2$ and ZrO$_2$) are different: A non-polar phase transforms into a polar phase by spontaneous inversion symmetry breaking upon the application of an electric field. Here, we show that this structural transition in antiferroelectric ZrO$_2$ gives rise to a negative capacitance, which is promising for overcoming the fundamental limits of energy efficiency in electronics. Our findings provide insight into the thermodynamically 'forbidden' region of the antiferroelectric transition in ZrO$_2$ and extend the concept of negative capacitance beyond ferroelectricity. This shows that negative capacitance is a more general phenomenon than previously thought and can be expected in a much broader range of materials exhibiting structural phase transitions

Albiglutide and cardiovascular outcomes in patients with type 2 diabetes and cardiovascular disease (Harmony Outcomes): a double-blind, randomised placebo-controlled trial

Background: Glucagon-like peptide 1 receptor agonists differ in chemical structure, duration of action, and in their effects on clinical outcomes. The cardiovascular effects of once-weekly albiglutide in type 2 diabetes are unknown. We aimed to determine the safety and efficacy of albiglutide in preventing cardiovascular death, myocardial infarction, or stroke. Methods: We did a double-blind, randomised, placebo-controlled trial in 610 sites across 28 countries. We randomly assigned patients aged 40 years and older with type 2 diabetes and cardiovascular disease (at a 1:1 ratio) to groups that either received a subcutaneous injection of albiglutide (30–50 mg, based on glycaemic response and tolerability) or of a matched volume of placebo once a week, in addition to their standard care. Investigators used an interactive voice or web response system to obtain treatment assignment, and patients and all study investigators were masked to their treatment allocation. We hypothesised that albiglutide would be non-inferior to placebo for the primary outcome of the first occurrence of cardiovascular death, myocardial infarction, or stroke, which was assessed in the intention-to-treat population. If non-inferiority was confirmed by an upper limit of the 95% CI for a hazard ratio of less than 1·30, closed testing for superiority was prespecified. This study is registered with ClinicalTrials.gov, number NCT02465515. Findings: Patients were screened between July 1, 2015, and Nov 24, 2016. 10 793 patients were screened and 9463 participants were enrolled and randomly assigned to groups: 4731 patients were assigned to receive albiglutide and 4732 patients to receive placebo. On Nov 8, 2017, it was determined that 611 primary endpoints and a median follow-up of at least 1·5 years had accrued, and participants returned for a final visit and discontinuation from study treatment; the last patient visit was on March 12, 2018. These 9463 patients, the intention-to-treat population, were evaluated for a median duration of 1·6 years and were assessed for the primary outcome. The primary composite outcome occurred in 338 (7%) of 4731 patients at an incidence rate of 4·6 events per 100 person-years in the albiglutide group and in 428 (9%) of 4732 patients at an incidence rate of 5·9 events per 100 person-years in the placebo group (hazard ratio 0·78, 95% CI 0·68–0·90), which indicated that albiglutide was superior to placebo (p<0·0001 for non-inferiority; p=0·0006 for superiority). The incidence of acute pancreatitis (ten patients in the albiglutide group and seven patients in the placebo group), pancreatic cancer (six patients in the albiglutide group and five patients in the placebo group), medullary thyroid carcinoma (zero patients in both groups), and other serious adverse events did not differ between the two groups. There were three (<1%) deaths in the placebo group that were assessed by investigators, who were masked to study drug assignment, to be treatment-related and two (<1%) deaths in the albiglutide group. Interpretation: In patients with type 2 diabetes and cardiovascular disease, albiglutide was superior to placebo with respect to major adverse cardiovascular events. Evidence-based glucagon-like peptide 1 receptor agonists should therefore be considered as part of a comprehensive strategy to reduce the risk of cardiovascular events in patients with type 2 diabetes. Funding: GlaxoSmithKline

Prospects of Ge-based metal-oxide semiconductor field-effect transistors and tunnel transistors for low power digital logic

Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2017.Cataloged from PDF version of thesis.Includes bibliographical references (pages 157-167).Moore's law has driven technological improvements for decades by halving the areal footprint of the transistor every two years and increasing the performance of making integrated circuits while reducing their cost. The ability to reduce the footprint of the device was enabled by advances in processing technology, novel materials and device design. As ever-smaller footprints are desired, power density limitations and performance degradation require more innovations on all fronts. Recently introduced improvements to integrated circuits are high-K and metal gate for MOSFETs (45-nm node onward), the FinFET (22-nm node onward) and air gaps between copper interconnects (14-nm node) illustrating that at every new technology node there needs to be a materials or process-related improvement to reduce power and maintain performance. Other approaches are also being explored or taken to further improve the MOSFET performance in future technology nodes, namely use of channel materials with higher carrier mobility such as SiGe and Ge for p-MOSFETs, III-V compound semiconductors for n-MOSFETs and steep subthreshold swing devices such as tunnel field effect transistors (TFETs). This work evaluates both approaches utilizing germanium (Ge) and strained-Ge as a material to understand the benefits and drawbacks to both approaches. Hypothetically, high carrier mobility and velocity channel materials can lower the overall power consumption because lower power supply voltage is required to obtain the same amount of current. Germanium and strained-Ge are candidates for the channel material of p-MOSFETs. MOSFETs made using Ge and strained-Ge as the channel material are evaluated based upon the ITRS roadmap requirements using experimental results in this work and data from literature. The approach for using TFETs was evaluated in this work also using germanium as a channel material. TFETs can have a steep subthreshold swing (SS), better than the minimum of 60 mV/decade at room temperature for a MOSFET, which also reduces the total power and supply voltage required for operation. The reduced SS is hypothetically achieved through the band-to-band tunneling which allows for the filtering of the Fermi-tail distribution of carriers. Experimentally, TFETs have not generally shown the steeper than Fermi-tail SS promised by the theory and this work uses both results from fabricated strained-Si/strained-Ge TFETs as well as modeling to explain why this has been the case. The challenges for both technologies are outlined in this thesis and suggestions are made on approaches to tackling their respective intrinsic problems from the point of view of Ge-based devices.by Winston Chern.Ph. D

Decision Making for Experiments: Using MOSFET Development as a Case Study

Presented on November 1, 2018 at 12:00 p.m.-1:30 p.m. in the Marcus Nanotechnology Building, Room 1117-1118, Georgia Tech.Winston Chern graduated from MIT with his PhD in Electrical Engineering and Computer Science in Feb. 2017 under the supervision of Dimitri Antoniadis and with his MS under Judy Hoyt. An expert in CMOS device integration, he worked at IBM T.J. Watson as a research intern and has won the best paper award in IEEE Electron Device Letters, the George E. Smith Award in 2015, and the Ernst Guillerman award for best master’s thesis in 2013. Winston currently holds 3 positions that focus on advancing the technology readiness of prototype devices, including work on transferring technologies from academia to foundries and national laboratories. His projects range from commercialization of field emitter arrays with Akintunde (Tayo) Akinwande at MIT, advanced device integration as a Staff per Diem at Draper Stark Research Laboratories, and advanced lithography and imaging work as a Research Engineer at Izentis LLC.Runtime: 57:41 minutesDecision making is not a topic commonly taught in academia, even though it is essential to researchers. This presentation gives an introduction on decision making in research and project management from the point of view of business and research projects. The goal is to provide a framework for beginning researchers on how to get from the start of a project towards achieving their longer-term goal. The concepts will be introduced from the point of view of running a development project in a business. Strategies to manage risk will be applied to the standard approach of breaking the problem down into the development of smaller components and to each individual component. Risk mitigation strategies will be applied to a framework on how to solve problems at the component level. All the concepts will be put together and differences between research and development will be highlighted. At the end, the concepts will be applied to the MOSFET development, as a case study, to show how one utilizes the proposed framework

Sweet’s Syndrome Arising in a Scar

Acute febrile neutrophilic dermatosis (Sweet’s syndrome) is an uncommon inflammatory cutaneous disorder. It presents with lesions which are tender, erythematous, edematous papules and under histologic examination show dense neutrophilic infiltration of the dermis. These lesions are often accompanied by leukocytosis and fever. This paper reports a unique case of acute febrile neutrophilic dermatosis presenting as a Koebner response to a linear scar

Temperature Effects on Gated Silicon Field Emission Array Performance

Silicon field emitter arrays (Si FEAs) are being explored as an electron source for vacuum channel transistors for high temperature electronics. Arrays of 1000 × 1000 silicon tip based gated field emitters were studied by measuring their electrical characteristics up to 40 V of DC gate bias with a 1.3 mA emission current at different temperatures from 25 to 400 °C. At ∼350 °C, residual gas analyzer measurements show that water desorption and carbon dioxide partial pressures increase significantly, the gate to emitter leakage current decreases by more than ten times, and the collector current increases by more than ten times. These improvements remained after heat-treatment but were then lost once the device was exposed to the atmosphere for several days. The improvements could be recovered upon additional baking suggesting that adsorbates (primarily water) on the surface affected field emission and surface leakage. It was also found that after heat-treatment, the electrical characteristics of the devices exhibited \u3c 3% variation in collector current at 40 V, which (without exposure to the atmosphere) can be termed as a weak temperature dependence. These results suggest that Si FEAs could be viable as a high temperature transistor

Comportement dynamique des paliers de vilebrequin : influence des defauts de forme et des mesalignements

SIGLECNRS T Bordereau / INIST-CNRS - Institut de l'Information Scientifique et TechniqueFRFranc

Simulation Modelling of Silicon Gated Field Emitter Based Electronic Circuits

Vacuum transistors (VTs) are promising candidates in electronics due to their fast response and ability to function in harsh environments. In this study, several oscillator and logic gate circuit simulations using VTs are demonstrated. Silicon-gated field emitter arrays (Si-GFEAs) with 1000 × 1000 arrays were used experimentally to create a VT model. First, transfer and output characteristics sweeps were measured, and based on those data, an LTspice vacuum transistor (VT) model was developed. Then, the model was used to develop Wein and Ring oscillator circuits. The circuits were analytically simulated using LTspice, where the collector bias voltage was 200 V DC, and the gate bias voltage was 30–40 V DC. The Wein oscillator circuit produced a frequency of 102 kHz with a magnitude of 26 Vpp. The Ring oscillator produced a frequency of 1.14 MHz with a magnitude of 4 Vpp. Furthermore, two logic circuits, NOR and NAND gates, were also demonstrated using LTspice modeling. These simulation results illustrate the feasibility of integrating VTs into functional integrated circuits and provide a design approach for future on-chip vacuum transistors applied in logic or radio-frequency (RF) devices