Efficient Decompression of Binary Encoded Balanced Ternary Sequences

International audienceA balanced ternary digit, known as a trit, takes its values in {-1, 0, 1}. It can be encoded in binary as {11, 00, 01} for direct use in digital circuits. In this correspondence, we study the decompression of a sequence of bits into a sequence of binary encoded balanced ternary digits. We first show that it is useless in practice to compress sequences of more than 5 ternary values. We then provide two mappings, one to map 5 bits to 3 trits and one to map 8 bits to 5 trits. Both mappings were obtained by human analysis and lead to Boolean implementations that compare quite favorably with others obtained by tweaking assignment or encoding optimization tools. However, mappings that lead to better implementations may be feasible

HLS-Based Methodology for Fast Iterative Development Applied to Elliptic Curve Arithmetic

International audienceHigh-Level Synthesis (HLS) is used by hardware developers to achieve higher abstraction in circuit descriptions. In order to shorten the hardware development time via HLS, we present an adjustment of the Iterative and Incremental Design (IID) methodology, frequently used in software development. In particular, our methodology is relevant for the development of applications with unusual complexity: the method was applied here to the development of large modular arithmetic, commonly used for cryptography applications (e.g., Elliptic Curves). Rapid feedback on circuit characteristics is used to evaluate deep architectural changes in short time, greatly reducing the time-to-market with respect to hand-made designs. In addition, our approach is highly flexible, since the same generic high-level description can be used to produce an entire set of circuits, each with different area/performance trade-offs. Thanks to the proposed approach, any change to the initial specification (e.g., the curve used) is also very fast, while it may require a large effort in the case of hand-made designs

Photoemission Spectroscopy and Atomic Force Microscopy Investigation of Vapor Phase Co-Deposited Silver/Poly(3-hexylthiophene) Composites

Nanocomposite matrices of silver/poly(3-hexylthiophene) (P3HT) were prepared in ultrahigh vacuum through vapor-phase co-deposition. Change in microstructure, chemical nature and electronic properties with increasing filler (Ag) content were investigated using in-situ XPS and UPS, and ambient AFM. At least two chemical binding states occur between Ag nanoparticles and sulfur in P3HT at the immediate contact layer but no evidence of interaction between Ag and carbon (in P3HT) was found. AFM images reveal a change in Ag nanoparticles size with concentration which modifies the microstructure and the average roughness of the surface. Under co-deposition, P3HT largely retains its conjugated structures, which is evidenced by the similar XPS and UPS spectra to those of P3HT films deposited on other substrates. We demonstrate here that the magnitude of the barrier height for hole injection and the position of the highest occupied band edge (HOB) with respect to the Fermi level of Ag can be controlled and changed by adjusting the metal (Ag) content in the composite. Furthermore, UPS reveals distinct features related to the C 2p (Sigma states) in the 5-12 eV regions, indicating the presence of ordered P3HT which is different from solution processed films.Comment: Scudier and Wei provided equal contributio

Hyperbranched Quasi-1D TiO2 Nanostructure for Hybrid Organic-Inorganic Solar Cells

The performance of hybrid solar cells is strongly affected by the device morphology. In this work we demonstrate a Poly(3-hexylthiophene-2,5-diyl)/TiO2 hybrid solar cell where the TiO2 photoanode comprises an array of tree-like hyperbranched quasi-1D nanostructures self-assembled from the gas phase. This advanced architecture enables us to increase the power conversion efficiency to over 1%, doubling the efficiency with respect to state of the art devices employing standard mesoporous titania photoanodes. This improvement is attributed to several peculiar features of this array of nanostructures: high interfacial area; increased optical density thanks to the enhanced light scattering; and enhanced crystallization of Poly(3-hexylthiophene-2,5-diyl) inside the quasi-1D nanostructure

Knowledge of obstetric fistula prevention amongst young women in urban and rural Burkina Faso: a cross-sectional study

Obstetric fistula is a sequela of complicated labour, which, if untreated, leaves women handicapped and socially excluded. In Burkina Faso, incidence of obstetric fistula is 6/10,000 cases amongst gynaecological patients, with more patients affected in rural areas. This study aims to evaluate knowledge on obstetric fistula among young women in a health district of Burkina Faso, comparing rural and urban communities. This cross-sectional study employed multi-stage sampling to include 121 women aged 18-20 years residing in urban and rural communities of Boromo health district. Descriptive statistics and multiple logistic regression analysis were used to compare differences between the groups and to identify predictors of observed knowledge levels. Rural women were more likely to be married (p<0.000) and had higher propensity to teenage pregnancy (p=0.006). The survey showed overall poor obstetric fistula awareness (36%). Rural residents were less likely to have adequate preventive knowledge than urban residents [OR=0.35 (95%-CI, 0.16–0.79)]. This effect was only slightly explained by lack of education [OR=0.41 (95%-CI, 0.18–0.93)] and only slightly underestimated due to previous pregnancy [OR=0.27 (95%-CI, 0.09–0.79)]. Media were the most popular source of awareness amongst urban young women in contrast to their rural counterparts (68% vs. 23%). Most rural young women became ‘aware’ through word-of-mouth (68% vs. 14%). All participants agreed that the hospital was safer for emergency obstetric care, but only 11.0% believed they could face pregnancy complications that would require emergency treatment. There is urgent need to increase emphasis on neglected health messages such as the risks of obstetric fistula. In this respect, obstetric fistula prevention programs need to be adapted to local contexts, whether urban or rural, and multi-sectoral efforts need to be exerted to maximise use of other sectoral resources and platforms, including existing routine health services and schools, to ensure sustainability of health literacy efforts

L'exploitation des stations de traitement des eaux usées des petites et moyennes collectivités

International audienceL'exploitation des stations de traitement des eaux usées des petites et moyennes collectivités : critères de choix des technologies, importance de l'exploitation, comparaisons selon les procédés et technicité à privilégier, l'exploitation du procédé Filtres Plantés de Roseaux (FPR)

High-level synthesis for fast generation of hardware accelerators under resource constraints

Dans le domaine du calcul générique, les circuits FPGA sont très attrayants pour leur performance et leur faible consommation. Cependant, leur présence reste marginale, notamment à cause des limitations des logiciels de développement actuels. En effet, ces limitations obligent les utilisateurs à bien maîtriser de nombreux concepts techniques. Ils obligent à diriger manuellement les processus de synthèse, de façon à obtenir une solution à la fois rapide et conforme aux contraintes des cibles matérielles visées.Une nouvelle méthodologie de génération basée sur la synthèse d'architecture est proposée afin de repousser ces limites. L'exploration des solutions consiste en l'application de transformations itératives à un circuit initial, ce qui accroît progressivement sa rapidité et sa consommation en ressources. La rapidité de ce processus, ainsi que sa convergence sous contraintes de ressources, sont ainsi garanties. L'exploration est également guidée vers les solutions les plus pertinentes grâce à la détection, dans les applications à synthétiser, des sections les plus critiques pour le contexte d'utilisation réel. Cette information peut être affinée à travers un scénario d'exécution transmis par l'utilisateur.Un logiciel démonstrateur pour cette méthodologie, AUGH, est construit. Des expérimentations sont menées sur plusieurs applications reconnues dans le domaine de la synthèse d'architecture. De tailles très différentes, ces applications confirment la pertinence de la méthodologie proposée pour la génération rapide et autonome d'accélérateurs matériels complexes, sous des contraintes de ressources strictes. La méthodologie proposée est très proche du processus de compilation pour les microprocesseurs, ce qui permet son utilisation même par des utilisateurs non spécialistes de la conception de circuits numériques. Ces travaux constituent donc une avancée significative pour une plus large adoption des FPGA comme accélérateurs matériels génériques, afin de rendre les machines de calcul simultanément plus rapides et plus économes en énergie.In the field of high-performance computing, FPGA circuits are very attractive for their performance and low consumption. However, their presence is still marginal, mainly because of the limitations of current development tools. These limitations force the user to have expert knowledge about numerous technical concepts. They also have to manually control the synthesis processes in order to obtain solutions both fast and that fulfill the hardware constraints of the targeted platforms.A novel generation methodology based on high-level synthesis is proposed in order to push these limits back. The design space exploration consists in the iterative application of transformations to an initial circuit, which progressively increases its rapidity and its resource consumption. The rapidity of this process, along with its convergence under resource constraints, are thus guaranteed. The exploration is also guided towards the most pertinent solutions thanks to the detection of the most critical sections of the applications to synthesize, for the targeted execution context. This information can be refined with an execution scenarion specified by the user.A demonstration tool for this methodology, AUGH, has been built. Experiments have been conducted with several applications known in the field of high-level synthesis. Of very differen sizes, these applications confirm the pertinence of the proposed methodology for fast and automatic generation of complex hardware accelerators, under strict resource constraints. The proposed methodology is very close to the compilation process for microprocessors, which enable it to be used even by users non experts about digital circuit design. These works constitute a significant progress for a broader adoption of FPGA as general-purpose hardware accelerators, in order to make computing machines both faster and more energy-saving