Influence of the sample geometry on the vortex matter in superconducting microstructures

The dependence of the vortex penetration and expulsion on the geometry of mesoscopic superconductors is reported. Hall magnetometry measurements were performed on a superconducting Al square and triangle. The stability of the vortex patterns imposed by the sample geometry is discussed. The field-temperature $H-T$ diagram has been reconstructed showing the transitions between states with different vorticity. We have found that the vortex penetration is only weakly affected by the vortex configuration inside the sample while the expulsion is strongly controlled by the stability of the vortex patterns. A qualitative explanation for this observation is given.Comment: 6 pages, 4 figures, accepted for publication in Phys. Rev.

Flux pinning by regular arrays of ferromagnetic dots

The pinning of flux lines by two different types of regular arrays of submicron magnetic dots is studied in superconducting Pb films; rectangular Co dots with in-plane magnetization are used as pinning centers to investigate the influence of the magnetic stray field of the dots on the pinning phenomena, whereas multilayered Co/Pt dots with out-of-plane magnetization are used to study the magnetic interaction between the flux lines and the magnetic moment of the dots. For both types of pinning arrays, matching anomalies are observed in the magnetization curves versus perpendicular applied field at integer and rational multiples of the first matching field, which correspond to stable flux configurations in the artificially created pinning potential. By varying the magnetic domain structure of the Co dots with in-plane magnetization, a clear influence of the stray field of the dots on the pinning efficiency is found. For the Co/Pt dots with out-of-plane magnetization, a pronounced field asymmetry is observed in the magnetization curves when the dots are magnetized in a perpendicular field prior to the measurement. This asymmetry can be attributed to the interaction of the out-of-plane magnetic moment of the Co/Pt dots with the local field of the flux lines and indicates that flux pinning is stronger when the magnetic moment of the dot and the field of the flux line have the same polarity.Comment: 7 pages including figures; submitted for publication in Physica C (Proceedings ESF-Vortex Conference, 18-24 Sept. 1999, Crete, Greece

Via patterning in the 7-nm node using immersion lithography and graphoepitaxy directed self-assembly

© 2017 Society of Photo-Optical Instrumentation Engineers (SPIE). Insertion of a graphoepitaxy directed self-assembly process as a via patterning technology into integrated circuit fabrication is seriously considered for the 7-nm node and beyond. At these dimensions, a graphoepitaxy process using a cylindrical block copolymer that enables hole multiplication can alleviate costs by extending 193-nm immersion-based lithography and significantly reducing the number of masks that would be required per layer. To be considered for implementation, it needs to be proved that this approach can achieve the required pattern quality in terms of defects and variability using a representative, aperiodic design. The patterning of a via layer from an actual 7-nm node logic layout is demonstrated using immersion lithography and graphoepitaxy directed self-assembly in a fab-like environment. The performance of the process is characterized in detail on a full 300-mm wafer scale. The local variability in an edge placement error of the obtained patterns (4.0 nm 3σ for singlets) is in line with the recent results in the field and significantly less than of the prepattern (4.9 nm 3σ for singlets). In addition, it is expected that pattern quality can be further improved through an improved mask design and optical proximity correction. No major complications for insertion of the graphoepitaxy directed self-assembly into device manufacturing were observed.status: publishe

Implementation of surface energy modification in grapho-epitaxy directed self-assembly for hole multiplication

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Influence of template fill in grapho-epitaxy DSA

Directed self-assembly (DSA) of block copolymers (BCP) is considered a promising patterning approach for the 7 nm node and beyond. Specifically, a grapho-epitaxy process using a cylindrical phase BCP may offer an efficient solution for patterning randomly distributed contact holes with sub-resolution pitches, such as found in via and cut mask levels. In any grapho-epitaxy process, the pattern density impacts the template fill (local BCP thickness inside the template) and may cause defects due to respectively over- or underfilling of the template. In order to tackle this issue thoroughly, the parameters that determine template fill and the influence of template fill on the resulting pattern should be investigated. In this work, using three process flow variations (with different template surface energy), template fill is experimentally characterized as a function of pattern density and film thickness. The impact of these parameters on template fill is highly dependent on the process flow, and thus pre-pattern surface energy. Template fill has a considerable effect on the pattern transfer of the DSA contact holes into the underlying layer. Higher fill levels give rise to smaller contact holes and worse critical dimension uniformity. These results are important towards DSA-aware design and show that fill is a crucial parameter in grapho-epitaxy DSA.status: publishe

EUV patterned templates with grapho-epitaxy DSA at the N5/N7 logic nodes

In this paper, approaches are explored for combining EUV with DSA for via layer patterning at the N7 and N5 logic nodes. Simulations indicate opportunity for significant LCDU improvement at the N7 node without impacting the required exposure dose. A templated DSA process based on NXE:3300 exposed EUV pre-patterns has been developed and supports the simulations. The main point of improvement concerns pattern placement accuracy with this process. It is described how metrology contributes to the measured placement error numbers. Further optimization of metrology methods for determining local placement errors is required. Next, also via layer patterning at the N5 logic node is considered. On top of LCDU improvement, the combination of EUV with DSA also allows for maintaining a single mask solution at this technology node, due to the ability of the DSA process to repair merging vias. It is experimentally shown, how shaping of templates for such via multiplication helps in placement accuracy control. Peanut-shaped pre-patterns, which can be printed using EUV lithography, give significantly better placement accuracy control compared to elliptical pre-patterns.status: publishe

Templated DSA vias in sub-7 nm circuits: Design strategy and DSA-aware via decomposition

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The world price of jump and volatility risk

We study international integration of markets for jump and volatility risk, using index option data for the main global markets. To explain the cross-section of expected option returns we focus on return-based multi-factor models. For each market separately, we provide evidence that volatility and jump risk are priced risk factors. There is little evidence, however, of global unconditional pricing of these risks. We show that UK and US option markets have become increasingly interrelated, and using conditional pricing models generates some evidence of international pricing. Finally, the benefits of diversifying jump and volatility risk internationally are substantial, but declining. Highlights ► Explain international equity index option returns with jump and volatility factors. ► We find strong evidence for local pricing of jump and volatility risk. ► We find much less evidence for global pricing of these factors. ► The US and UK option markets have become increasingly interrelated. ► There are substantial benefits to internationally diversifying option investments

Process optimization of templated DSA flows

Directed Self-Assembly (DSA) of Block Co-Polymers (BCP) has become an intense field of study as a potential patterning solution for future generation devices. The most critical challenges that need to be understood and controlled include pattern placement accuracy, achieving low defectivity in DSA patterns and how to make chip designs DSA-friendly. The DSA program at imec includes efforts on these three major topics. Specifically, in this paper the progress in setting up flows for templated DSA within the imec program will be discussed. A process has been implemented based on a hard mask as the template layer. In this paper primarily the impact of local pattern density and BCP film thickness on the templated DSA process are discussed. The open hole rate and the placement accuracy of BCP patterns within the template are the primary figures of merit.. © 2014 SPIE.status: publishe