NONLINEAR OPERATORS FOR IMAGE PROCESSING: DESIGN, IMPLEMENTATION AND MODELING TECHNIQUES FOR POWER ESTIMATION

1998/1999Negli ultimi anni passati le applicazioni multimediali hanno visto uno sviluppo notevole, trovando applicazione in un gran numero di campi. Applicazioni come video conferenze, diagnostica medica, telefonia mobile e applicazioni militari necessitano il trattamento di una gran mole di dati ad alta velocità. Pertanto, l'elaborazione di immagini e di dati vocali è molto importante ed è stata oggetto di numerosi sforzi, nel tentativo di trovare algoritmi sempre più veloci ed efficaci. Tra gli algoritmi proposti, noi crediamo che gli operatori razionali svolgano un ruolo molto importante, grazie alla loro versatilità ed efficacia nell'elaborazione di dati. Negli ultimi anni sono stati proposti diversi algoritmi, dimostrando che questi operatori possono essere molto vantaggiosi in diverse applicazioni, producendo buoni risultati. Lo scopo di questo lavoro è di realizzare alcuni di questi algoritmi e, quindi, dimostrare che i filtri razionali, in particolare, possono essere realizzati senza ricorrere a sistemi di grandi dimensioni e possono raggiungere frequenze operative molto alte. Una volta che il blocco fondamentale di un sistema basato su operatori razionali sia stato realizzato, esso pu6 essere riusato con successo in molte altre applicazioni. Dal punto di vista del progettista, è importante avere uno schema generale di studio, che lo renda capace di studiare le varie configurazioni del sistema da realizzare e di analizzare i compromessi tra le variabili di progetto. In particolare, per soddisfare l'esigenza di metodi versatili per la stima della potenza, abbiamo sviluppato una tecnica di macro modellizazione che permette al progettista di stimare velocemente ed accuratamente la potenza dissipata da un circuito. La tesi è organizzata come segue: Nel Capitolo 1 alcuni sono presentati alcuni algoritmi studiati per la realizzazione. Ne viene data solo una veloce descrizione, lasciando comunque al lettore interessato dei riferimenti bibliografici. Nel Capitolo 2 vengono discusse le architetture fondamentali usate per la realizzazione. Principalmente sono state usate architetture a pipeline, ma viene data anche una descrizione degli approcci oggigiorno disponibili per l'ottimizzazione delle temporizzazioni. Nel Capitolo 3 sono presentate le realizzazioni di due sistemi studiati per questa tesi. Gli approcci seguiti si basano su ASIC e FPGA. Richiedono tecniche e soluzioni diverse per il progetto del sistema, per cui é interessante vedere cosa pu6 essere fatto nei due casi. Infine, nel Capitolo 4, descriviamo la nostra tecnica di macro modellizazione per la stima di potenza, dando una breve visione delle tecniche finora proposte e facendo vedere quali sono i vantaggi che il nostro metodo comporta per il progetto.In the past few years, multimedia application have been growing very fast, being applied to a large variety of fields. Applications like video conference, medical diagnostic, mobile phones, military applications require to handle large amount of data at high rate. Images as well as voice data processing are therefore very important and they have been subjected to a lot of efforts in order to find always faster and effective algorithms. Among image processing algorithms, we believe that rational operators assume an important role, due to their versatility and effectiveness in data processing. In the last years, several algorithms have been proposed, demonstrating that these operators can be very suitable in different applications with very good results. The aim of this work is to implement some of these algorithm and, therefore, demonstrate that rational filters, in particular, can be implemented without requiring large sized systems and they can operate at very high frequencies. Once the basic building block of a rational based system has been implemented, it can be successfully reused in many other applications. From the designer point of view, it is important to have a general framework, which makes it able to study various configurations of the system to be implemented and analyse the trade-off among the design variables. In particular, to meet the need far versatile tools far power estimation, we developed a new macro modelling technique, which allows the designer to estimate the power dissipated by a circuit quickly and accurately. The thesis is organized as follows: In chapter 1 we present some of the algorithms which have been studied for implementation. Only a brief overview is given, leaving to the interested reader some references in literature. In chapter 2 we discuss the basic architectures used for the implementations. Pipelined structures have been mainly used for this thesis, but an overview of the nowaday available approaches for timing optimization is presented. In chapter 3 we present two of the implementation designed for this thesis. The approaches followed are ASIC driven and FPGA drive. They require different techniques and different solution for the design of the system, therefore it is interesting to see what can be done in both the cases. Finally, in chapter 4, we describe our macro modelling techniques for power estimation, giving a brief overview of the up to now proposed techniques and showing the advantages our method brings to the design.XII Ciclo1969Versione digitalizzata della tesi di dottorato cartacea

Regulation of OPA1 processing and mitochondrial fusion by m-AAA protease isoenzymes and OMA1

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Analytical Macromodeling for High-Level Power Estimation

This paper presents a new macromodeling technique for high-level power estimation. Our technique is based on a parameterizable analytical model that relies exclusively on statistical information of the circuit's primary inputs. During estimation, the statistics of the required metrics are extracted from the input stream, and a power estimate is obtained by evaluating a model function that has been characterized in advance. Our model yields power estimates within seconds, because it does not rely on the statistics of the circuit's primary outputs and, consequently, does not perform any simulation during estimation. Moreover, it achieves better accuracy than previous macromodeling approaches by taking into account both spatial and temporal correlations in the input stream. In experiments with the ISCAS-85 combinational circuits, the average absolute relative error of our power macromodeling technique was at most 1.8%. The worst-case error was at most 12.8%. For a ripple-carry adder fami..

Hardware Implementation Of The Median-Rational Hybrid Filters For Colour Images

A new class of nonlinear Filters called Vector Median Rational Hybrid Filter (VMRHF) [1][2] has been recently introduced and applied to colour image filtering problems. As shown in these papers, hybrid filters exhibit very desirable filtering features which often outperform those of the components of the hybrid filter itself. The VMRHF filter is a two-stage filter, which exploits the features of the vector-median filter and those of the rational operator. The performances of the proposed filter are compared with those of the Vector Median Filter (VMF), described in [3], and of the Directional-Distance Filter (DDF), reported in [4]. In this paper we also present a hardware implementation of the VMRHF which exploits in an effective way the features and the robustness of both median filters and rational filters. This architecture is suitable for the use in real-time applications due to its reduced hardware complexity. 1. MEDIAN-RATIONAL HYBRID FILTERS The Vector Median Rational Filter is ..

An ASIC for multichannel data acquisition systems

In this paper, we describe the realization of an ASIC which may signi"cantly simplify the instrumental apparatus for measures in UHV (ultra-high vacuum, p410~9 mbar) while permitting very fast acquisitions. The chip will "rst be used in ESCA experiments; however, its parallel architecture and the fast serial protocol for data transmission may increase the e$ciency of the measure process in any experiment where multichannel acquisition is a key issue

An Asic For Multichannel Data Acquisition Systems

In this paper we describe the realization of an ASIC which may significantly simplify the instrumental apparatus for measures in UHV (ultra-high vacuum, p 10 \Gamma9 mbar) while permitting very fast acquisitions. The chip will first be used in ESCA experiments; however, its parallel architecture and the fast serial protocol for data transmission may increase the efficiency of the measure process in any experiment where multichannel acquisition is a key issue. Classification codes and keywords 07.05.Hd; 07.85.Qe; 39.30.+w; 07.50.-e ASIC, parallel readout detectors, multichannel acquisition systems, UHV environment, synchrotron light sources, ESCA. 1 Introduction The recent availability of third generation synchrotron radiation sources is opening many new opportunities in the field of experimental physics. These opportunities, however, can be exploited only if suitable new acquisition hardware is developed [1]. A fundamental acquisition improvement is given by the use of paralle..