S-Net for multi-memory multicores

Copyright ACM, 2010. This is the author's version of the work. It is posted here by permission of ACM for your personal use. Not for redistribution. The definitive version was published in Proceedings of the 5th ACM SIGPLAN Workshop on Declarative Aspects of Multicore Programming: http://doi.acm.org/10.1145/1708046.1708054S-Net is a declarative coordination language and component technology aimed at modern multi-core/many-core architectures and systems-on-chip. It builds on the concept of stream processing to structure dynamically evolving networks of communicating asynchronous components. Components themselves are implemented using a conventional language suitable for the application domain. This two-level software architecture maintains a familiar sequential development environment for large parts of an application and offers a high-level declarative approach to component coordination. In this paper we present a conservative language extension for the placement of components and component networks in a multi-memory environment, i.e. architectures that associate individual compute cores or groups thereof with private memories. We describe a novel distributed runtime system layer that complements our existing multithreaded runtime system for shared memory multicores. Particular emphasis is put on efficient management of data communication. Last not least, we present preliminary experimental data

A Case Study in Coordination Programming: Performance Evaluation of S-Net vs Intel's Concurrent Collections

We present a programming methodology and runtime performance case study comparing the declarative data flow coordination language S-Net with Intel's Concurrent Collections (CnC). As a coordination language S-Net achieves a near-complete separation of concerns between sequential software components implemented in a separate algorithmic language and their parallel orchestration in an asynchronous data flow streaming network. We investigate the merits of S-Net and CnC with the help of a relevant and non-trivial linear algebra problem: tiled Cholesky decomposition. We describe two alternative S-Net implementations of tiled Cholesky factorization and compare them with two CnC implementations, one with explicit performance tuning and one without, that have previously been used to illustrate Intel CnC. Our experiments on a 48-core machine demonstrate that S-Net manages to outperform CnC on this problem.Comment: 9 pages, 8 figures, 1 table, accepted for PLC 2014 worksho

Strategy Switching: Smart Fault-Tolerance for Weakly-Hard Resource-Constrained Real-Time Applications

The probability of data corruption as a result of single event upsets (SEUs) increases as transistor sizes decrease. Software-based fault-tolerance can help offer protection against SEUs on Commercial off The Shelf (COTS) hardware. However, such fault tolerance relies on replication, for which there may be insufficient resources in resource-constrained environments. Systems in the weakly-hard real-time domain can tolerate some faults as a product of their domain. Combining both the need for fault-tolerance and the intrinsic ability to tolerate faults, we propose a new approach for applying fault-tolerance named strategy switching. Strategy switching minimizes the effective unmitigated fault-rate by switching which tasks are to be run under a fault-tolerance scheme at runtime. Our method does not require bounding the number of faults for a given number of consecutive iterations.We show how our method improves the steady-state fault rate by analytically computing the rate for our test set of generated DAGs and comparing this against a static application of fault-tolerance. Finally, we validate our method using UPPAAL.</p