An adaptive pattern recognition hardware with on-chip shift register-based partial reconfiguration

A pattern recognition system that can process a large amount of image data at high speed is required in many fields. In this paper, we propose an on-chip pattern recognition system that utilizes the reconfig-urability of the FPGA. The features of the system are not only very high recognition speed but also an adap-tive function. For example, when objects to be de-tected change appearance, recognition parameters must be changed to retain the recognition accuracy. The system can automatically adjust by executing on-chip partial reconfiguration. The system runs at 25MHz and can return a recognition result in one clock cycle, 40ns. To update the system, all processes needed for searching for the best recognition parameters, gener-ating configuration data and reconfiguring the system are carried out within 30s. 1

共鳴増幅配線による低損失伝送線の開発

科学研究費助成事業 研究成果報告書：基盤研究(B)2014-2016課題番号 : 2628911

An Online EHW Pattern Recognition System Applied to Face Image Recognition

Abstract. An evolvable hardware (EHW) architecture for high-speed pattern recognition has been proposed. For a complex face image recognition task, the system demonstrates (in simulation) an accuracy of 96.25% which is better than previously proposed EHW architectures. In contrast to previous approaches, this architecture is designed for online evolution. Incremental evolution and high level modules have been utilized in order to make the evolution feasible.