Monolithic Active Pixel Matrix with Binary Counters (MAMBO) ASIC

Monolithic Active Matrix with Binary Counters (MAMBO) is a counting ASIC designed for detecting and measuring low energy X-rays from 6-12 keV. Each pixel contains analogue functionality implemented with a charge preamplifier, CR-RC{sup 2} shaper and a baseline restorer. It also contains a window comparator which can be trimmed by 4 bit DACs to remove systematic offsets. The hits are registered by a 12 bit ripple counter which is reconfigured as a shift register to serially output the data from the entire ASIC. Each pixel can be tested individually. Two diverse approaches have been used to prevent coupling between the detector and electronics in MAMBO III and MAMBO IV. MAMBO III is a 3D ASIC, the bottom ASIC consists of diodes which are connected to the top ASIC using {mu}-bump bonds. The detector is decoupled from the electronics by physically separating them on two tiers and using several metal layers as a shield. MAMBO IV is a monolithic structure which uses a nested well approach to isolate the detector from the electronics. The ASICs are being fabricated using the SOI 0.2 {micro}m OKI process, MAMBO III is 3D bonded at T-Micro and MAMBO IV nested well structure was developed in collaboration between OKI and Fermilab

A vertically integrated pixel readout device for the Vertex Detector at the International Linear Collider

3D-Integrated Circuit technology enables higher densities of electronic circuitry per unit area without the use of nanoscale processes. It is advantageous for mixed mode design with precise analog circuitry because processes with conservative feature sizes typically present lower process dispersions and tolerate higher power supply voltages, resulting in larger separation of a signal from the noise floor. Heterogeneous wafers (different foundries or different process families) may be combined with some 3D integration methods, leading to the optimization of each tier in the 3D stack. Tracking and vertexing in future High-Energy Physics (HEP) experiments involves construction of detectors composed of up to a few billions of channels. Readout electronics must record the position and time of each measurement with the highest achievable precision. This paper reviews a prototype of the first 3D readout chip for HEP, designed for a vertex detector at the International Linear Collider. The prototype features 20 x 20 {micro}m{sup 2} pixels, laid out in an array of 64 x 64 elements and was fabricated in a 3-tier 0.18 {micro}m Fully Depleted SOI CMOS process at MIT-Lincoln Laboratory. The tests showed correct functional operation of the structure. The chip performs a zero-suppressed readout. Successive submissions are planned in a commercial 3D bulk 0.13 {micro}m CMOS process to overcome some of the disadvantages of an FDSOI process

Vertically integrated pixel readout chip for high energy physics

We report on the development of the vertex detector pixel readout chips based on multi-tier vertically integrated electronics for the International Linear Collider. Some testing results of the VIP2a prototype are presented. The chip is the second iteration of the silicon implementation of the prototype, data-pushed concept of the readout developed at Fermilab. The device was fabricated in the 3D MIT-LL 0.15 {micro}m fully depleted SOI process. The prototype is a three-tier design, featuring 30 x 30 {micro}m{sup 2} pixels, laid out in an array of 48 x 48 pixels

Spontaneous and reversible hollowing of alloy anode nanocrystals for stable battery cycling

ISSN:1748-3387ISSN:1748-339

Vertically Integrated Circuits at Fermilab

The exploration of the vertically integrated circuits, also commonly known as 3D-IC technology, for applications in radiation detection started at Fermilab in 2006. This paper examines the opportunities that vertical integration offers by looking at various 3D designs that have been completed by Fermilab. The emphasis is on opportunities that are presented by through silicon vias (TSV), wafer and circuit thinning and finally fusion bonding techniques to replace conventional bump bonding. Early work by Fermilab has led to an international consortium for the development of 3D-IC circuits for High Energy Physics. The consortium has submitted over 25 different designs for the Fermilab organized MPW run organized for the first time

FPHX: A New Silicon Strip Readout Chip for the PHENIX Experiment at RHIC

The FPHX chip is a silicon strip readout chip developed at Fermilab for use in the FVTX Detector of the PHENIX experiment at RHIC. Each front end consists of an integrator which is AC coupled to a shaper, followed by a discriminator and a 3-bit analog-to-digital converter. The backend is a novel architecture in two stages that permits dead-timeless operation and high-speed readout with very low latency. A slow controller provides an interface for all on-chip programmable functions. This chip has been fabricated in the 0.25um TSMC process. All functionality including the analog front-end, the digital back-end, and the slow controller has been verified experimentally

3D design activities at Fermilab: Opportunities for physics

Fermilab began exploring the technologies for vertically integrated circuits (also commonly known as 3D circuits) in 2006. These technologies include through silicon vias (TSV), circuit thinning, and bonding techniques to replace conventional bump bonds. Since then, the interest within the High Energy Physics community has grown considerably. This paper will present an overview of the activities at Fermilab over the last 3 years which have helped spark this interest