77 research outputs found

    Reliability analysis of planar and symmetrical & asymmetrical trench discrete SiC Power MOSFETs

    Get PDF
    Silicon Carbide MOSFETs are shown in research to outperform Silicon counterparts on many performance metrics, including switching rates and power losses. To further improve their performance, trench and double-trench structures have recently been developed. To replace conventional planar SiC MOSFETs, besides the performance parameters which are mostly stated in datasheets, reliability studies under stress are also needed. This thesis presents a comprehensive comparison between 3rd generation trench SiC power MOSFETs, namely symmetrical double-trench and asymmetrical trench with planar SiC power MOSFETs on four aspects of: switching slew rates (dI/dt & dV/dt), crosstalk characteristics, bias temperature instability and power cycling stability.First, the dynamic performance in both 1st quadrant and 3rd quadrant has been eval- uated on the differences in stress by dI/dt & dV/dt and resultant losses. This is key in understanding many other reliability criterions, i.e. severity of crosstalk induced switchings. In the 1st quadrant, the source current and drain-source voltage switching rates at both turn-ON and turn-OFF are measured under a range of test conditions. Both the symmetrical and asymmetrical trench MOSFETs have up to 2 times faster voltage and current slew rates compared with the planar one. They also indicate only slight changes in switching rate with junction temperature. In the 3rd quadrant, the reverse recovery peak current and total reverse recovery charge are measured with respect to junction temper- ature and load current level. Both the symmetrical and asymmetrical trench MOSFETs have less than half of the reverse recovery charge of that of the planar SiC MOSFET.In the evaluation of crosstalk characteristics, peak shoot-through current and induced gate voltage at crosstalk are measured with respect to junction temperature and external gate resistance. With particularly large external gate resistances connected to intentionally induce parasitic turn-ON, the symmetrical double-trench MOSFET is shown to be more prone to crosstalk with 23 A peak shoot-through current measured while it is only 10 A for asymmetrical trench and 4 A for planar MOSFET under similar test conditions. As the temperature increase, the peak shoot-through current drops for the symmetrical double-trench, while constant for the asymmetrical trench and rising for the planar device.Threshold voltage drift is also measured to reflect the degradation happened with bias temperature instability at various junction temperatures, stressing voltages and time periods. Under low-magnitude gate stress (within the range of datasheets) in both positive and negative bias cases, there is more threshold drift observed on the two trench MOSFETs at all junction temperatures than the planar MOSFET. When the stress magnitude is raised, there is less threshold drift observed on the two trench MOSFETs.To evaluate the ruggedness in continuous switchings, the devices are placed under repetitive turn-ON events. The thermal performance under such operation are compared. The asymmetrical trench MOSFET experiences the highest case temperature rise while the least is observed for the planar MOSFET. With an external heatsink equipped to achieve more efficient cooling, the repetitive turn-ON test transforms into the conventional power cycling. In this condition, both the symmetrical and asymmetrical trench MOSFETs fail earlier than the degraded (but not failed) planar MOSFET

    Electrothermal Power Cycling to Failure of Discrete Planar, Symmetrical Double-Trench and Asymmetrical Trench SiC MOSFETs

    Get PDF
    While SiC MOSFETs are now being utilized in industry their robustness under heavy-duty applications still remains a concern. In this paper, the results of experimental measurements of degradation to failure of different structured SiC power MOSFETs, namely the planar, symmetrical double-trench and asymmetrical trench structures are presented following electrothermal stressing by power cycling to beyond the safe operating area (SOA) limits. The tests are categorised in to subsets with/without forced cooling. The first set of tests involve successive switchings of the devices under constant DC current supply while their case temperature is monitored in real-time to evaluate their thermal performance. The symmetrical double-trench and asymmetrical trench MOSFETs are found to experience a higher case temperature rise thus prone to breakdown while failure is not observed in the planar structured device. The second experiment stresses the devices during continuous power cyclings with force cooling applied, in which the symmetrical and asymmetrical double-trench MOSFETs still encounter failure with detectable breakdown on the gate oxides, compared with the planar device which only exhibits degradation, without failure, with indications of aging

    FakeLocator: Robust Localization of GAN-Based Face Manipulations

    Full text link
    Full face synthesis and partial face manipulation by virtue of the generative adversarial networks (GANs) and its variants have raised wide public concerns. In the multi-media forensics area, detecting and ultimately locating the image forgery has become an imperative task. In this work, we investigate the architecture of existing GAN-based face manipulation methods and observe that the imperfection of upsampling methods therewithin could be served as an important asset for GAN-synthesized fake image detection and forgery localization. Based on this basic observation, we have proposed a novel approach, termed FakeLocator, to obtain high localization accuracy, at full resolution, on manipulated facial images. To the best of our knowledge, this is the very first attempt to solve the GAN-based fake localization problem with a gray-scale fakeness map that preserves more information of fake regions. To improve the universality of FakeLocator across multifarious facial attributes, we introduce an attention mechanism to guide the training of the model. To improve the universality of FakeLocator across different DeepFake methods, we propose partial data augmentation and single sample clustering on the training images. Experimental results on popular FaceForensics++, DFFD datasets and seven different state-of-the-art GAN-based face generation methods have shown the effectiveness of our method. Compared with the baselines, our method performs better on various metrics. Moreover, the proposed method is robust against various real-world facial image degradations such as JPEG compression, low-resolution, noise, and blur.Comment: 16 pages, accepted to IEEE Transactions on Information Forensics and Securit

    Impact of Temperature and Switching Rate on Properties of Crosstalk on Symmetrical & Asymmetrical Double-trench SiC Power MOSFET

    Get PDF
    In this paper, the properties of crosstalk on SiC planar MOSFET, SiC symmetrical double-trench MOSFET and SiC asymmetrical double-trench MOSFET is investigated on a half-bridge topology, to enable analysis of the impact of temperature, drain-source transition speed and gate resistance on the severity of the shoot-through current and induced gate voltage. The experimental measurements, performed on a wide range of temperatures and switching rates, show that the two selected symmetrical and asymmetrical double-trench MOSFETs exhibit higher induced gate voltage during crosstalk with the same external gate resistance compared with the planar SiC MOSFET, yielding a higher shoot-through current. Therefore, in continuous initiation of intentional crosstalk, the two double-trench MOSFETs experience more temperature rise, especially for symmetrical one which leads the device to verge of failure within minutes while the temperature rise in other two devices is significantly lower. The different trends of shoot-through current with temperature on DUTs reveals that they are dominated by different mechanisms, i.e., influenced by threshold voltage and inversion layer carriers’ mobility. A model is developed for prediction of shoot-through current during crosstalk which is validated for the 3 device structures. The comparison of the modelled results with the measurement proves its capability to predict the crosstalk behaviour
    • …
    corecore