Radiation effects in high speed III-V integrated circuits

The article of record as published may be found at http://dx.doi.org/10.1142/S0129156403001612International Journal of High Speed Electronics and Systems, v. 13, p. 277 (2003).The types of applications affected by radiation effects in W-V devices have significantly changed over the last four decades. For most applications W-V ICs have provided sufficient radiation hardness. Some expectations for hardened soft error applications did not materialize until much later. Years of research defined that not only material properties. but device structures. layout practices and circuit design influenced how m-v devices were susceptible to certain radiation effects. The highest performance ill-V ICs due to their low power-speed energy products will provide challenges in ionizing radiation environments from sea level to space

SEE analysis of digital InP-based HBT circuits at gigahertz frequencies

The article of record as published may be found at http://dx.doi.org/10.1109/23.983160IEEE Transactions on Nuclear Science, V. 48, No. 6, pp. 1980-1986, December 2001A device/circuit simulation is used to analyze a gigahertz clocked emitter-coupled logic circuit being perturbed by a single event. Results provide an understanding of charge collection in the heterojunction bipolar transistor. A technique for single-event hardening is demonstrated by simulation

Historical perspective on radiation effects in III–V devices

The article of record as published may be found at http://dx.doi.org/10.1109/TNS.2003.813124A historical review of radiation effects on III–V semiconductor devices is presented. The discussion ranges from examining early material and device studies to present-day understanding of III–V radiation effects. The purpose of this paper is to provide present researchers with a summary of discoveries and lessons learned from previous failures and successes

Doping-Assisted Defect Control In Compound Semiconductors

PatentThe present invention relates to the production of thin film epilayers of III-V and other compounds with acceptor doping wherein the acceptor thermally stabilizes the epilayer, stabilize the naturally incorporated native defect population and therewith maintain the epilayer's beneficial properties upon annealing among other advantageous effects. In particular, balanced doping in which the acceptor concentration is similar to (but does not exceed) the antisite defects in the as-grown material is shown to be particularly advantageous in providing thermal stability, high resistivity and ultrashort trapping times. In particular, MBE growth of LT-GaAs epilayers with balanced Be doping is described in detail. The growth conditions greatly enhance the materials reproducibility (that is, the yield in processed devices). Such growth techniques can be transferred to other III-V materials if the growth conditions are accurately reproduced. Materials produced herein also demonstrate advantages in reproducibility, reliability and radiation hardening

SEU design considerations for MESFETs on LT GaAs

The article of record as published may be found at http://dx.doi.org/10.1109/23.659047IEEE Transactions on Nuclear Science, V. 44, No. 6, pp. 2282-2289, December 1997Computer simulation results are reported on transistor design and single-event charge collection modeling of metal­ semiconductor field effect transistors (MESFETs) fabricated in the Vitesse H-GaAsIII® process on Low Temperature grown (LT) GaAs epitaxial layers. Tradeoffs in Single Event Upset (SEU) immunity and transistor design are discussed. Effects due to active loads and diffusion barriers are examined.U.S. Navy Space and Naval Warfare Systems Comman

Modeling single-event effects in a complex digital device

The article of record as published may be found at http://dx.doi.org/10.1109/TNS.2003.821793IEEE Transactions on Nuclear Science, V. 50, No. 6, pp. 2069-2080, December 2003A methodology to quantify the impact of SEEs on complex digital devices has been developed. This methodology is based on the SEE State-Transition Model and was validated by radiation testing of a complex digital device

Absolute potential measurements inside microwave digital IC's using a micromachined photoconductive sampling probe

The article of record as published may be found at http://dx.doi.org/10.1109/22.739220A measurement system for internal node testing of integrated circuits using a micromachined photoconductive sampling probe is described and characterized. Special emphasis is placed upon the system performance, demonstrating how absolute voltage measurements are achieved in a dc-to-mm-wave bandwidth. The feasibility of the setup is illustrated using an InP heterojunction bipolar transistor frequency divider. Detailed waveforms at different circuit nodes and the corresponding propagation delays from within this circuit at operating frequencies up to 10 GHz are presented. The results demonstrate for the first time the use of photoconductive probes for calibration-free, absolute-voltage, dc-coupled potential measurements in high-frequency and high-speed integrated circuits.This work was sponsored by the National Science Foundation through the Center for Ultrafast Optical Science by the AFOSR, Air Force Materiel Command, USAF and by the U.S. NavySTC PHY 8920108, Grant DOD-G-F49620-95-1-0027, Contract N62271-97-M-131