Tuning contact resistance in top-contact p-type and n-type organic field effect transistors by self-generated interlayers

\u3cp\u3eContact resistance significantly limits the performance of organic field-effect transistors (OFETs). Positioning interlayers at the metal/organic interface can tune the effective work-function and reduce contact resistance. Myriad techniques offer interlayer processing onto the metal pads in bottom-contact OFETs. However, most methods are not suitable for deposition on organic films and incompatible with top-contact OFET architectures. Here, a simple and versatile methodology is demonstrated for interlayer processing in both p- and n-type devices that is also suitable for top-contact OFETs. In this approach, judiciously selected interlayer molecules are co-deposited as additives in the semiconducting polymer active layer. During top contact deposition, the additive molecules migrate from within the bulk film to the organic/metal interface due to additive-metal interactions. Migration continues until a thin continuous interlayer is completed. Formation of the interlayer is confirmed by X-ray photoelectron spectroscopy (XPS) and cross-section scanning transmission electron microscopy (STEM), and its effect on contact resistance by device measurements and transfer line method (TLM) analysis. It is shown that self-generated interlayers that reduce contact resistance in p-type devices, increase that of n-type devices, and vice versa, confirming the role of additives as interlayer materials that modulate the effective work-function of the organic/metal interface.\u3c/p\u3

Short-channel vertical organic field-effect transistors with high on/off ratios

\u3cp\u3e A unique vertical organic field-effect transistor structure in which highly doped silicon nanopillars are utilized as a gate electrode is demonstrated. An additional dielectric layer, partly covering the source, suppresses bulk conduction and lowers the OFF current. Using a semiconducting polymer as active channel material, short-channel (100 nm) transistors with ON/OFF current ratios up to 10 \u3csup\u3e6\u3c/sup\u3e are realized. The electronic behavior is explained using space-charge and contact-limited current models and numerical simulations. The current density and switching speed of the devices are in the order of 0.1 A cm \u3csup\u3e−2\u3c/sup\u3e and 0.1 MHz, respectively, at biases of only a few volts. These characteristics make the devices very promising for applications where large current densities, high switching speeds, and high ON/OFF ratios are required. \u3c/p\u3

Submicrometer top-gate self-aligned a-IGZO TFTs by substrate conformal imprint lithography

\u3cp\u3e Thin-film transistors (TFTs) are the fundamental building blocks of today's display industry. To achieve higher drive currents and device density, it is essential to scale down the channel lengths of TFTs. To be able to fabricate short-channel TFTs in large volumes is also equally important in order to realize lower fabrication costs and higher throughput. In this paper, we demonstrate the application of substrate conformal imprint lithography (SCIL) to pattern top-gate (TG) self-aligned (SA) amorphous indium gallium zinc oxide TFTs down to channel length L \u3csub\u3eG\u3c/sub\u3e = 450 nm with good device scaling properties resulting in average field-effect mobility (μ \u3csub\u3eFE\u3c/sub\u3e ) = ∼ 10 cm \u3csup\u3e2\u3c/sup\u3e ·V \u3csup\u3e-1\u3c/sup\u3e ·s \u3csup\u3e-1\u3c/sup\u3e , V \u3csub\u3eON\u3c/sub\u3e = ∼ 0.5 V, and subthreshold swing (SS) = ∼ 0.3 V/decade. The device performance as a function of channel length outlines the importance of dopant diffusion control for realizing submicrometer SA TFTs. The results demonstrate the compatibility of SCIL-based large-area patterning for the realization of submicrometer TG SA TFTs with a potential for high throughput. \u3c/p\u3

Low-cost monolithic processing of large-area ultrasound transducer arrays

\u3cp\u3eLarge-area flexible ultrasound arrays can offer new ultrasound modalities in multiple fields. The production of these arrays when using CMOS-type fabrication techniques faces scalability challenges and costs increase dramatically when upscaled to large dimensions. We investigate the monolithic production of large-area PPT (Printed Polymer Transducer) arrays directly on a flexible substrate. Here, a vibrating membrane is defined by a circular opening in a thick photoresist layer. Since the photoresist layer is processed on top of the P(VDF-TrFE), a thin barrier layer is used to prevent diffusion into the P(VDF-TrFE). An annealing procedure is developed to reduce the surface roughness of the P(VDF-TrFE) layer and make it compatible with thin film electrode deposition. We measure a remnant polarization of 7-8 μC/cm\u3csup\u3e2\u3c/sup\u3e and a coercive field of around 50 MV/m. Laser scanning vibrometer measurements reveal a uniform peak displacement and fundamental resonance frequency (66 kHz) across the PPT array.\u3c/p\u3

Photosensitivity in Epilepsy Syndromes:Age Differences?

The presence of paroxysmal abnormalities of brain electrical activity provoked by intermittent photic stimulation, is an age-dependent EEG pattern usually first seen in childhood and adolescence. Indirect evidence suggests that this maps onto the time-course of the maturation of excitatory and inhibitory brain systems. Recent studies have confirmed the role of abnormal gating mechanisms in the abnormal susceptibility of the posterior cortex to visual stimuli in young patients with photosensitive epilepsy. Similarly, the later maturation of the parvocellular systems which has been associated with the photoparoxysmal EEG response might account for the low prevalence of photosensitivity in the very young patients. From the clinical perspective, while photosensitivity has a preferential onset in pediatric age, it tends to persist in adulthood, with two-thirds of the patients continuing to show the EEG trait even though 85% of them will no longer experience overt clinical seizures. The data presented in this chapter give an account of the role of maturational progression in the manifestations of photosensitivity at mesoscopic level and their integration with genetic data might provide a clearer account of the variability in genotype/phenotype association seen in photosensitive patients

Power saving through state retention in IGZO-TFT AMOLED displays for wearable applications

\u3cp\u3eWe present a qHD (960 × 540 with three sub-pixels) top-emitting active-matrix organic light-emitting diode display with a 340-ppi resolution using a self-aligned IGZO thin-film transistor backplane on polyimide foil with a humidity barrier. The back plane process flow is based on a seven-layer photolithography process with a CD = 4 μm. We implement a 2T1C pixel engine and use a commercial source driver IC made for low-temperature polycrystalline silicon. By using an IGZO thin-film transistor and leveraging the extremely low off current, we can switch off the power to the source and gate driver while maintaining the image unchanged for several minutes. We demonstrate that, depending on the image content, low-refresh operation yields reduction in power consumption of up to 50% compared with normal (continuous) operation. We show that with the further increase in resolution, the power saving through state retention will be even more significant.\u3c/p\u3

Power saving through state retention in IGZO-TFT AMOLED displays for wearable applications

\u3cp\u3eWe present a qHD (960×540 with 3 sub-pixels) top-emitting ‘AMOLED display with 340ppi resolution using a self-aligned (SA) IGZO TFT backplane on polyimidefoil with humidity barrier. The back plane process flow is based on a 7 layer photolithography process with a CD=4um. We implement a 2TIC pixel engine and use commercial source driver IC made for LTPS. By using IGZO TFT and leveraging the extremely low off-current, we can switch-offthe power to the source and gate driver while maintaining the image un-changed for several minutes We demonstrate that, depending on the image content, low-refresh operation yields reduction in power consumption of up to 50% compared to normal (continuous) operation. We show that with further increase in resolution, the power saving through state retention will be even more significant.\u3c/p\u3

Dual-gate self-aligned IGZO TFTs monolithically integrated with high-temperature bottom moisture barrier for flexible AMOLED

\u3cp\u3eWe present a 350°C self-aligned dual-gate a-IGZO backplane technology with a monolithically integrated multi-layer high-temperature thin-film barrier for flexible AMOLED. Thin-film barrier properties and TFT technology are optimized on 320 x 352mm substrates, and demonstrated in a flexible QQVGA 100 ppi AMOLED display prototype.\u3c/p\u3