Specific mapping of disease resistance genes in tetraploid cut roses

Control of fungal diseases is a major constraint of cut-rose cultivation in greenhouses and in transportation around the world. Therefore, development of resistant cultivars is a promising way to reduce the use of chemicals required for controlling the diseases. Genetic analyses and breeding for resistance, however, are hampered by the high degree of heterozygosity and the polyploid nature of cultivated roses. Nucleotide-binding site (NBS) profiling of Van der Linden et al. (2004) was used as a tool enabling a more directed way of studying the genetics of resistance to pathogens responsible for diseases such as powdery mildew. NBS profiling is a multiplex screening technique, producing amplified resistance gene (R-gene) and resistance gene analogue (RGA) fragments by using degenerated primers based on the conserved motifs present in the NBS domain of resistance genes. Since RGAs are abundantly distributed and highly polymorphic within the plant genome, NBS profiling generates multiple markers of putative resistance genes. Twelve NBS degenerated primer/ restriction enzyme combinations were used to genotype the whole rose tetraploid K5 population (Yan, 2005) and its parents. To generate RGA profiles, the restriction enzymes: AluI, HaeIII, Mse and RsaI were used in combination with degenerated primers NBS1, NBS3, and NBS5a6. The profiles were dominantly scored resulting in 106 polymorphic RGA markers which segregated in a 1:1 or 3:1 ratio. Uni-and bi-parental simplex markers will be mapped on the two available AFLP/SSR K5 maps (Yan, 2005) with Joinmap 4.0. The resulting parental tetraploid maps will be used to dissect the genetic variation for resistance to powdery mildew resistance. Additional Rosaceae SSRs mentioned in the literature are currently tested on the K5 population to obtain allelic bridges between the tetraploid and diploid genetic maps in rose and related species in order to align them. These bridges will improve cross-ploidy comparisons in roses in order to strengthen cut rose breedin

A Single-Trim frequency reference system with 0.7 ppm/°C from −63 °C to 165 °C Consuming 210 μW at 70 MHz

This article presents a frequency reference system that combines high frequency accuracy and low power consumption using a single-point temperature trim and batch calibration. The system is intended as a low-cost fully integrated crystal oscillator replacement. In this system, the oscillation frequency of a power-efficient, but process, voltage, temperature (PVT) and lifetime (L)-sensitive current-controlled ring oscillator (CCO) is periodically (re)calibrated by the well-behaved frequency stability of an untuned LC -based Colpitts oscillator (LCO), which is optimized for stability over PVT variations and lifetime (PVTL). During the single-point room temperature factory trim, the frequency of the LCO is determined and the result is digitally stored. An on-chip calibration engine tunes the CCO to the target frequency based on the LCO frequency, temperature sensor information, and digitally stored trimming information, thus effectively improving the frequency stability of the ring oscillator. The relatively high-power LCO is heavily duty-cycled to minimize the overall power consumption. A prototype fabricated in a 0.13- μ m high-voltage (HV) CMOS SOI process and assembled in a plastic package demonstrates an inaccuracy lower than ±93 ppm over a temperature range from -63 °C to 165 °C across 18 samples. The presented frequency reference system, including on-chip voltage regulators and a temperature sensor, occupies a chip area of 0.69 mm2 and consumes about 64 μA from a single 3.3-V supply. The frequency error due to supply variation is roughly 92 ppm/V. The mean frequency shift due to aging, measured before and after a six-day storage bake at 175 °C, is only 52 ppm.</p

65-micron thin monocrystalline silicon solar cell technology allowing 12-fold reduction in silicon usage

Thin (<70 micron) single crystal silicon solar cells have been manufactured through the use of a novel process involving selective etching. Narrow grooves are micromachined through the wafer using a standard micromachining technique with cells manufactured on the resulting silicon strips. These bifacial cells have a much greater surface area than the original wafer, leading to dramatic decreases in processing effort and silicon usage. Individual cells fabricated using the new process have displayed efficiencies up to 17.5% while a 560cm2 prototype module has displayed an efficiency of 12.3%. The size, thickness and bifacial nature of the cells offer the opportunity for a wide variety of module architectures and applications