Rede : gehalten in der feierlichen Versammlung des paedagogischen Central-Instituts

Rede über das Studium der orientalischen Sprachen

Real-Time Data Processing in the Muon System of the D0 Detector

This paper presents a real-time application of the 16-bit fixed point Digital Signal Processors (DSPs), in the Muon System of the D0 detector located at the Fermilab Tevatron, presently the world's highest-energy hadron collider. As part of the Upgrade for a run beginning in the year 2000, the system is required to process data at an input event rate of 10 KHz without incurring significant deadtime in readout. The ADSP21csp01 processor has high I/O bandwidth, single cycle instruction execution and fast task switching support to provide efficient multisignal processing. The processor's internal memory consists of 4K words of Program Memory and 4K words of Data Memory. In addition there is an external memory of 32K words for general event buffering and 16K words of Dual Port Memory for input data queuing. This DSP fulfills the requirement of the Muon subdetector systems for data readout. All error handling, buffering, formatting and transferring of the data to the various trigger levels of the data acquisition system is done in software. The algorithms developed for the system complete these tasks in about 20 microseconds per event.Comment: 4 pages, Presented and published at the 11th IEEE NPSS Real Time Conference, held at Santa Fe, New Mexico, USA, from June 14-18, 199

GPS навигация для мобильных робототехнических систем

There is a multitude of ways in which mobile robotic system can orient itself in a

A 3-D Track-Finding Processor for the CMS Level-1 Muon Trigger

We report on the design and test results of a prototype processor for the CMS Level-1 trigger that performs 3-D track reconstruction and measurement from data recorded by the cathode strip chambers of the endcap muon system. The tracking algorithms are written in C++ using a class library we developed that facilitates automatic conversion to Verilog. The code is synthesized into firmware for field-programmable gate-arrays from the Xilinx Virtex-II series. A second-generation prototype has been developed and is currently under test. It performs regional track-finding in a 60 degree azimuthal sector and accepts 3 GB/s of input data synchronously with the 40 MHz beam crossing frequency. The latency of the track-finding algorithms is expected to be 250 ns, including geometrical alignment correction of incoming track segments and a final momentum assignment based on the muon trajectory in the non-uniform magnetic field in the CMS endcaps.Comment: 7 pages, 5 figures, proceedings for the conference on Computing in High Energy and Nuclear Physics, March 24-28 2003, La Jolla, Californi

Origin and Loss of Nested LRRTM/alpha-Catenin Genes during Vertebrate Evolution

Peer reviewe

Mechanochemical synthesis of carbon-based nanocomposites for supercapacitors

New nanoporous carbon-SiO2 composite materials were synthesized from organic raw materials (rice shells) and their electrochemical properties were investigated by cyclic voltammetry in liquid electrolytes (6 M KOH or 1 M H2SO4). A correlation between specific capacitance and specific surface area was observed. Due to high specific capacitance of 90 F/g the carbon materials under study may be regarded as promising electrode materials for electrochemical supercapacitors