Foodborne norovirus outbreak: the role of an asymptomatic food handler

Background: In July 2005 an outbreak of acute gastroenteritis occurred on a residential summer camp in the province of Barcelona (northeast of Spain). Forty-four people were affected among residents and employees. All of them had in common a meal at lunch time on 13 July (paella, round of beef and fruit). The aim of this study was to investigate a foodborne norovirus outbreak that occurred in the residential summer camp and in which the implication of a food handler was demonstrated by laboratory tests. Methods: A retrospective cohort study was designed. Personal or telephone interview was carried out to collect demographic, clinical and microbiological data of the exposed people, as well as food consumption in the suspected lunch. Food handlers of the mentioned summer camp were interviewed. Ten stool samples were requested from symptomatic exposed residents and the three food handlers that prepared the suspected food. Stools were tested for bacteries and noroviruses. Norovirus was detected using RT-PCR and sequence analysis. Attack rate, relative risks (RR) and its 95% confidence intervals (CI) were calculated to assess the association between food consumption and disease. Results: The global attack rate of the outbreak was 55%. The main symptoms were abdominal pain (90%), nausea (85%), vomiting (70%) and diarrhoea (42.5%). The disease remitted in 24-48 hours. Norovirus was detected in seven faecal samples, one of them was from an asymptomatic food handler who had not eaten the suspected food (round of beef), but cooked and served the lunch. Analysis of the two suspected foods isolated no pathogenic bacteria and detected no viruses. Molecular analysis showed that the viral strain was the same in ill patients and in the asymptomatic food handler (genotype GII.2 Melksham-like). Conclusions: In outbreaks of foodborne disease, the search for viruses in affected patients and all food handlers, even in those that are asymptomatic, is essential. Health education of food handlers with respect to hand washing should be promoted

Simultaneous Multithreaded Vector Architecture: Merging ILP and DLP for High Performance

The goal of this paper is to show that instruction level parallelism (ILP) and data-level parallelism (DLP) can be merged in a single simultaneous vector multithreaded architecture to execute regular vectorizable code at a performance level that can not be achieved using either paradigm on its own. We will show that the combination of the two techniques yields very high performance at a low cost and a low complexity: We will show that this architecture achieves a sustained performance on numerical regular codes that is 20 times the performance that can be achieved with today's superscalar microprocessors. Moreover, we will show that the architecture can tolerate very large memory latencies, of up to a 100 cycles, with a relatively small performance degradation. This high performance is independent of working set size or of locality considerations, since the DLP paradigm allows very efficient exploitation of a high performance flat memory bandwidth. 1 Introduction Future high performan..

Performance Advantages of Merging Instruction- and Data-Level Parallelism

This paper presents a new architecture based on addding a vector pipeline to a superscalar microprocessor. The goal of this paper is to show that instruction-level parallelism (ILP) and data-level parallelism (DLP) can be merged in a single architecture to execute regular vectorizable code at a performance level that can not be achieved using only ILP techniques. We present an analysis of the two paradigms at the instruction set architecture (ISA) level that shows that the DLP model has several advantages: executes fewer instructions, fewer overall operations (by factors as large as 1.7), and generally executes fewer memory accesses. We then analyze the ILP model in terms of IPC. Our simulations show that a 4-way machine achieves IPCs in the range 1.03-1.52 and that by scaling to 16-way, only a 26% of the peak IPC is achieved. The combined ILP+DLP model, on the contrary, is shown to perform from 1.24 to 2.84 times better than the 4-way ILP machine. Moreover, when we scale up the ILP+DL..

A Case for Merging the ILP and DLP Paradigms

The goal of this paper is to show that instruction level parallelism (ILP) and data-level parallelism (DLP) can be merged in a stngle architecture to ezecute vectorizable code at a performance level that can not be achieved using either paradigm on its own. We will show that the combination of the two techniques yields very high performance at a low cost and a low complexity. We will show that this architecture can reach a performance equivalent to a supers calar processor that sustained 10 instructions per cycle. We will see that the machine exploiting both types of paralleiism improves upon the IL P-only machine by factors of 1.5–1.8. We also present a study on the scalability of both paradigms and show that, when we increase resources to reach a 16-issue machine, the advantage of the IL P+DLP machine over the IL P-only machine increases up to 2.0-3.45. Whiie the peak achieved IPC for the ILP machine is 4, the ILP+DLP machine exceeds 10 instructions per cycle.

Out-of-Order Vector Architectures

Register renaming and out-of-order instruction issue are now commonly used in superscalar processors. These techniques can also be used to significant advantage in vector processors, as this paper shows. Performance is improved and available memory bandwidth is used more effectively. Using a trace driven simulation for a vectorizable subset of the Perfect Club and Specfp92 programs we compare a conventional vector implementation, based on the Convex C3400 with an out-of-order, register renaming, vector implementation. When the number of physical registers is above 12, out-of-order execution coupled with register renaming provides a speedup of 1.24--1.72 for realistic memory latencies. With an ideal memory system with no latency, there is still a speedup of as much as 1.15--1.25. When memory latencies are varied, using out-of-order techniques allows much more latency tolerance than traditional vector implementations. Memory latencies of 100 cycles generally result in performance degrada..