INVESTIGATING THE EXPERIENCES OF STUDENTS WITH DISABILITIES WITH E-LEARNING DURING THE COVID-19 PANDEMIC IN VIETNAMESE HIGHER EDUCATION

This study uses a mixed-methods approach to investigate the experiences of Vietnamese university students with disabilities (visual/mobility impairments) with e-learning as a consequence of emergency remote teaching during the COVID-19 pandemic. An analysis of the ideas of 20 surveyed students with disabilities at eight universities in Ho Chi Minh City and six students interviewed afterward shows that students can change their study habits to adapt to e-learning and to enjoy this model of learning. However, the participants revealed that they also want to experience face-to-face learning so that they can interact with their lecturers and peers more effectively and in more diverse ways, as well as assimilate lectures more easily. Furthermore, the research shows that various adjustments should be made by system designers, universities, and lecturers to make e-learning friendlier to disabled students. The recommended adjustments include designing easy-to-use learning tools and platforms, providing lecturers with the necessary tools and facilities to design lessons appropriate for all students, providing psychological and technical support for disabled students, choosing user-friendly learning applications and platforms, providing students with suitable learning resources, and modifying testing and assessment methods

NHÂN GIỐNG LAN GIẢ HẠC (Dendrobium anosmum) ĐỘT BIẾN BẰNG PHƯƠNG PHÁP NUÔI CẤY IN VITRO

Currently, mutant orchids are very interested in orchid lovers who want to collect, but the price of mutant orchids is costly leading to many orchid lovers are unable to own it. This study aims to create mutant orchid plantlets with high quantity and low cost via in vitro propagation method. From the self-pollinated six months old seedpods, we have successfully propagated the orchid mutant seedlings. The results showed that the suitable medium for mutant orchid seed germination and creating protocorm was the basic MS medium supplemented with 0.5 mg/L BA with a rate of up to 93%. The medium for shoot formation and shoot development from protocorm was the best on MS medium added with 1.0 mg/L BA and 0.5 mg/L IBA with a rate of 88%. The rooting induction was 99.06% and the root length reached 5.34 cm with an average of 8.53 roots/shoot when shoots cultured on MS medium supplemented with 1.0 mg/L NAA. The survival rate of in vitro Dendrobium anosmum mutant seedlings after 60 days in the nursery stage was 84.9% on coir and rice husks substrates (1:1).Hiện nay, hoa lan đột biến đang trở thành tâm điểm được nhiều người quan tâm sưu tầm, nhưng do giá thành cây giống quá cao nên rất ít người có thể sở hữu. Để tạo ra giống với số lượng lớn, rẻ thì việc nhân giống in vitro những giống lan này là cần thiết. Vì vậy, từ vật liệu khởi đầu là quả lan sáu tháng tuổi tự thụ phấn từ cây mẹ đột biến, chúng tôi đã xây dựng thành công quy trình nhân giống lan Giả hạc đột biến bằng phương pháp nuôi cấy in vitro. Kết quả cho thấy môi trường thích hợp cho hạt lan đột biến nảy mầm tạo protocorm là môi trường MS cơ bản, bổ sung 0,5 mg/L N6-benzyladenine (BA) với tỷ lệ 93%. Môi trường thích hợp để protocorm tạo chồi là MS cơ bản, bổ sung 1,0 mg/L BA và 0,5 mg/L indole 3-butyric acid (IBA) với tỷ lệ tạo chồi 88%, chiều cao và số lá trên chồi trung bình 1,42 cm và 2,4 lá. Môi trường tối ưu để chồi tạo cây hoàn chỉnh là môi trường MS cơ bản, bổ sung 1,0 mg/L naphthaleneacetic acid (NAA) với tỷ lệ 99,06% chồi ra rễ; chiều dài rễ đạt 5,34 cm với trung bình 8,53 rễ/chồi. Tỷ lệ sống của cây con in vitro đột biến sau 60 ngày ra vườn ươm là 84,9% trên giá thể xơ dừa và trấu hun (1:1)

Mise en oeuvre matérielle de décodeurs LDPC haut débit, en exploitant la robustesse du décodage par passage de messages aux imprécisions de calcul

The increasing demand of massive data rates in wireless communication systems will require significantly higher processing speed of the baseband signal, as compared to conventional solutions. This is especially challenging for Forward Error Correction (FEC) mechanisms, since FEC decoding is one of the most computationally intensive baseband processing tasks, consuming a large amount of hardware resources and energy. The conventional approach to increase throughput is to use massively parallel architectures. In this context, Low-Density Parity-Check (LDPC) codes are recognized as the foremost solution, due to the intrinsic capacity of their decoders to accommodate various degrees of parallelism. They have found extensive applications in modern communication systems, due to their excellent decoding performance, high throughput capabilities, and power efficiency, and have been adopted in several recent communication standards.This thesis focuses on cost-effective, high-throughput hardware implementations of LDPC decoders, through exploiting the robustness of message-passing decoding algorithms to computing inaccuracies. It aims at providing new approaches to cost/throughput optimizations, through the use of imprecise computing and storage mechanisms, without jeopardizing the error correction performance of the LDPC code. To do so, imprecise processing within the iterative message-passing decoder is considered in conjunction with the quantization process that provides the finite-precision information to the decoder. Thus, we first investigate a low complexity code and decoder aware quantizer, which is shown to closely approach the performance of the quantizer with decision levels optimized through exhaustive search, and then propose several imprecise designs of Min-Sum (MS)-based decoders. Proposed imprecise designs are aimed at reducing the size of the memory and interconnect blocks, which are known to dominate the overall area/delay performance of the hardware design. Several approaches are proposed, which allow storing the exchanged messages using a lower precision than that used by the processing units, thus facilitating significant reductions of the memory and interconnect blocks, with even better or only slight degradation of the error correction performance.We propose two new decoding algorithms and hardware implementations, obtained by introducing two levels of impreciseness in the Offset MS (OMS) decoding: the Partially OMS (POMS), which performs only partially the offset correction, and the Imprecise Partially OMS (I-POMS), which introduces a further level of impreciseness in the check-node processing unit. FPGA implementation results show that they can achieve significant throughput increase with respect to the OMS, while providing very close decoding performance, despite the impreciseness introduced in the processing units.We further introduce a new approach for hardware efficient LDPC decoder design, referred to as Non-Surjective Finite-Alphabet Iterative Decoders (FAIDs). NS-FAIDs are optimized by Density Evolution for regular and irregular LDPC codes. Optimization results reveal different possible trade-offs between decoding performance and hardware implementation efficiency. To validate the promises of optimized NS-FAIDs in terms of hardware implementation benefits, we propose three high-throughput hardware architectures, integrating NS-FAIDs decoding kernels. Implementation results on both FPGA and ASIC technology show that NS-FAIDs allow significant improvements in terms of both throughput and hardware resources consumption, as compared to the Min-Sum decoder, with even better or only slightly degraded decoding performance.Les codes correcteurs d'erreurs sont une composante essentielle de tout système de communication, capables d’assurer le transport fiable de l’information sur un canal de communication bruité. Les systèmes de communication de nouvelle génération devront faire face à une demande sans cesse croissante en termes de débit binaire, pouvant aller de 1 à plusieurs centaines de gigabits par seconde. Dans ce contexte, les codes LDPC (pour Low-Density Parity-Check, en anglais), sont reconnus comme une des solutions les mieux adaptées, en raison de la possibilité de paralléliser massivement leurs algorithmes de décodage et les architectures matérielles associées. Cependant, si l’utilisation d’architectures massivement parallèles permet en effet d’atteindre des débits très élevés, cette solution entraine également une augmentation significative du coût matériel.L’objectif de cette thèse est de proposer des implémentations matérielles de décodeurs LDPC très haut débit, en exploitant la robustesse des algorithmes de décodage par passage de messages aux imprécisions de calcul. L’intégration dans le décodage itératif de mécanismes de calcul imprécis, s’accompagne du développement de nouvelles approches d’optimisation du design en termes de coût, débit et capacité de correction.Pour ce faire, nous avons considéré l’optimisation conjointe de (i) le bloc de quantification qui fournit l'information à précision finie au décodeur, et (ii) les unités de traitement imprécis des données, pour la mise à jour des messages échangés pendant de processus de décodage. Ainsi, nous avons tout d’abord proposé un quantificateur à faible complexité, qui peut être optimisé par évolution de densité en fonction du code LDPC utilisé et capable d’approcher de très près les performances d’un quantificateur optimal. Le quantificateur proposé a été en outre optimisé et utilisé pour chacun des décodeurs imprécis proposés ensuite dans cette thèse.Nous avons ensuite proposé, analysé et implémenté plusieurs décodeurs LDPC imprécis. Les deux premiers décodeurs sont des versions imprécises du décodeur « Offset Min-Sum » (OMS) : la surestimation des messages des nœuds de contrôle est d’abord compensée par un simple effacement du bit de poids faible (« Partially OMS »), ensuite le coût matériel est d’avantage réduit en supprimant un signal spécifique (« Imprecise Partially OMS »). Les résultats d’implémentation sur cible FPGA montrent une réduction importante du coût matériel, tout en assurant une performance de décodage très proche du OMS, malgré l'imprécision introduite dans les unités de traitement.Nous avions ensuite introduit les décodeurs à alphabet fini non-surjectifs (NS-FAIDs, pour « Non-Surjective Finite Alphabet Iterative Decoders », en anglais), qui étendent le concept d’« imprécision » au bloc mémoire du décodeur LDPC. Les décodeurs NS-FAIDs ont été optimisés par évolution de densité pour des codes LDPC réguliers et irréguliers. Les résultats d'optimisation révèlent différents compromis possibles entre la performance de décodage et l'efficacité de la mise en œuvre matérielle. Nous avons également proposé trois architectures matérielles haut débit, intégrant les noyaux de décodage NS-FAID. Les résultats d’implémentation sur cible FPGA et ASIC montrent que les NS-FAIDs permettent d’obtenir des améliorations significatives en termes de coût matériel et de débit, par rapport au décodeur Min-Sum, avec des performances de décodage meilleures ou très légèrement dégradées

Efficient Hardware Implementations of LDPC Decoders, through Exploiting Impreciseness in Message-Passing Decoding Algorithms

Les codes correcteurs d'erreurs sont une composante essentielle de tout système de communication, capables d’assurer le transport fiable de l’information sur un canal de communication bruité. Les systèmes de communication de nouvelle génération devront faire face à une demande sans cesse croissante en termes de débit binaire, pouvant aller de 1 à plusieurs centaines de gigabits par seconde. Dans ce contexte, les codes LDPC (pour Low-Density Parity-Check, en anglais), sont reconnus comme une des solutions les mieux adaptées, en raison de la possibilité de paralléliser massivement leurs algorithmes de décodage et les architectures matérielles associées. Cependant, si l’utilisation d’architectures massivement parallèles permet en effet d’atteindre des débits très élevés, cette solution entraine également une augmentation significative du coût matériel.L’objectif de cette thèse est de proposer des implémentations matérielles de décodeurs LDPC très haut débit, en exploitant la robustesse des algorithmes de décodage par passage de messages aux imprécisions de calcul. L’intégration dans le décodage itératif de mécanismes de calcul imprécis, s’accompagne du développement de nouvelles approches d’optimisation du design en termes de coût, débit et capacité de correction.Pour ce faire, nous avons considéré l’optimisation conjointe de (i) le bloc de quantification qui fournit l'information à précision finie au décodeur, et (ii) les unités de traitement imprécis des données, pour la mise à jour des messages échangés pendant de processus de décodage. Ainsi, nous avons tout d’abord proposé un quantificateur à faible complexité, qui peut être optimisé par évolution de densité en fonction du code LDPC utilisé et capable d’approcher de très près les performances d’un quantificateur optimal. Le quantificateur proposé a été en outre optimisé et utilisé pour chacun des décodeurs imprécis proposés ensuite dans cette thèse.Nous avons ensuite proposé, analysé et implémenté plusieurs décodeurs LDPC imprécis. Les deux premiers décodeurs sont des versions imprécises du décodeur « Offset Min-Sum » (OMS) : la surestimation des messages des nœuds de contrôle est d’abord compensée par un simple effacement du bit de poids faible (« Partially OMS »), ensuite le coût matériel est d’avantage réduit en supprimant un signal spécifique (« Imprecise Partially OMS »). Les résultats d’implémentation sur cible FPGA montrent une réduction importante du coût matériel, tout en assurant une performance de décodage très proche du OMS, malgré l'imprécision introduite dans les unités de traitement.Nous avions ensuite introduit les décodeurs à alphabet fini non-surjectifs (NS-FAIDs, pour « Non-Surjective Finite Alphabet Iterative Decoders », en anglais), qui étendent le concept d’« imprécision » au bloc mémoire du décodeur LDPC. Les décodeurs NS-FAIDs ont été optimisés par évolution de densité pour des codes LDPC réguliers et irréguliers. Les résultats d'optimisation révèlent différents compromis possibles entre la performance de décodage et l'efficacité de la mise en œuvre matérielle. Nous avons également proposé trois architectures matérielles haut débit, intégrant les noyaux de décodage NS-FAID. Les résultats d’implémentation sur cible FPGA et ASIC montrent que les NS-FAIDs permettent d’obtenir des améliorations significatives en termes de coût matériel et de débit, par rapport au décodeur Min-Sum, avec des performances de décodage meilleures ou très légèrement dégradées.The increasing demand of massive data rates in wireless communication systems will require significantly higher processing speed of the baseband signal, as compared to conventional solutions. This is especially challenging for Forward Error Correction (FEC) mechanisms, since FEC decoding is one of the most computationally intensive baseband processing tasks, consuming a large amount of hardware resources and energy. The conventional approach to increase throughput is to use massively parallel architectures. In this context, Low-Density Parity-Check (LDPC) codes are recognized as the foremost solution, due to the intrinsic capacity of their decoders to accommodate various degrees of parallelism. They have found extensive applications in modern communication systems, due to their excellent decoding performance, high throughput capabilities, and power efficiency, and have been adopted in several recent communication standards.This thesis focuses on cost-effective, high-throughput hardware implementations of LDPC decoders, through exploiting the robustness of message-passing decoding algorithms to computing inaccuracies. It aims at providing new approaches to cost/throughput optimizations, through the use of imprecise computing and storage mechanisms, without jeopardizing the error correction performance of the LDPC code. To do so, imprecise processing within the iterative message-passing decoder is considered in conjunction with the quantization process that provides the finite-precision information to the decoder. Thus, we first investigate a low complexity code and decoder aware quantizer, which is shown to closely approach the performance of the quantizer with decision levels optimized through exhaustive search, and then propose several imprecise designs of Min-Sum (MS)-based decoders. Proposed imprecise designs are aimed at reducing the size of the memory and interconnect blocks, which are known to dominate the overall area/delay performance of the hardware design. Several approaches are proposed, which allow storing the exchanged messages using a lower precision than that used by the processing units, thus facilitating significant reductions of the memory and interconnect blocks, with even better or only slight degradation of the error correction performance.We propose two new decoding algorithms and hardware implementations, obtained by introducing two levels of impreciseness in the Offset MS (OMS) decoding: the Partially OMS (POMS), which performs only partially the offset correction, and the Imprecise Partially OMS (I-POMS), which introduces a further level of impreciseness in the check-node processing unit. FPGA implementation results show that they can achieve significant throughput increase with respect to the OMS, while providing very close decoding performance, despite the impreciseness introduced in the processing units.We further introduce a new approach for hardware efficient LDPC decoder design, referred to as Non-Surjective Finite-Alphabet Iterative Decoders (FAIDs). NS-FAIDs are optimized by Density Evolution for regular and irregular LDPC codes. Optimization results reveal different possible trade-offs between decoding performance and hardware implementation efficiency. To validate the promises of optimized NS-FAIDs in terms of hardware implementation benefits, we propose three high-throughput hardware architectures, integrating NS-FAIDs decoding kernels. Implementation results on both FPGA and ASIC technology show that NS-FAIDs allow significant improvements in terms of both throughput and hardware resources consumption, as compared to the Min-Sum decoder, with even better or only slightly degraded decoding performance

High Throughput FPGA Implementation for regular Non-Surjective Finite Alphabet Iterative Decoders

International audience—This paper deals with the recently introduced class of Non-Surjective Finite Alphabet Iterative Decoders (NS-FAIDs). First, optimization results for an extended class of regular NS-FAIDs are presented. They reveal different possible trade-offs between decoding performance and hardware implementation efficiency. To validate the promises of optimized NS-FAIDs in terms of hardware implementation benefits, we propose two high-throughput hardware architectures, integrating NS-FAIDs decoding kernels. Implementation results show that NS-FAIDs allow significant improvements in terms of both throughput and hardware resources consumption, as compared to a baseline Min-Sum decoder, with even better or only slightly degraded decoding performance

Code-aware quantizer design for finite-precision min-sum decoders

International audienceClassically, the quantization of the soft information supplied to a finite-precision decoder is chosen to optimize a certain criterion which does not depend on the characteristics of the existing code. This work studies code-aware quantizers, for finite-precision min-sum decoders, which optimize the noise threshold of the existing family of Low-Density Parity-Check (LDPC) codes. We propose a code-aware quantizer with lower complexity than that obtained by optimizing all decision levels and approaching its performance, for few quantization bits. We show that code-aware quantizers outperform code-independent quantizers in terms of noise threshold for both regular and irregular LDPC codes. To overcome the error floor behavior of LDPC codes, we propose the design of the quantizer for a target error probability at the decoder output. The results show that the quantizer optimized to get a zero error probability could lead to a very bad performance for practical range of signal to noise ratios. Finally, we propose to design jointly irregular LDPC codes and code-aware quantizers for finite-precision min-sum decoders. We show that they achieve significant decoding gains with respect to LDPC codes designed for infinite-precision belief propagation decoding, but decoded by finite-precision min-sum

Performance evaluation of faulty iterative decoders using absorbing Markov chains

International audienc

Non-surjective finite alphabet iterative decoders

International audienceThis paper introduces a new theoretical framework, akin to the use of imprecise message storage in Low Density Parity Check (LDPC) decoders, which is seen as an enabler for cost-effective hardware designs. The proposed framework is the one of Non-Surjective Finite Alphabet Iterative Decoders (NS-FAIDs), and it is shown to provide a unified approach for several designs previously proposed in the literature. NS-FAIDs are optimized by density evolution for WiMAX irregular LDPC codes and we show they provide different trade-offs between hardware complexity and decoding performance. In particular, we derive a set of 27 NS-FAIDs that provide decoding gains up to 0.36 dB, while yielding a memory / interconnect reduction up to 25% / 30% compared to the Min-Sum decoder

Analysis and Design of Cost-Effective, High-Throughput LDPC Decoders

International audienc

Adaptive response of <i>Pseudomonas aeruginosa</i> under serial ciprofloxacin exposure

Supplementary Material for 'Adaptive response of Pseudomonas aeruginosa under serial ciprofloxacin exposure', as described in Microbiology. Understanding the evolution of antibiotic resistance is important for combating drug-resistant bacteria. In this work, we investigated the adaptive response of Pseudomonas aeruginosato ciprofloxacin. Ciprofloxacin-susceptible P. aeruginosa ATCC 9027, CIP-E1 which was exposed to ciprofloxacin for 14 days and CIP-E2 strain which was CIP-E1 cultured in antibiotic-free broth for 10 days were comparatively analyzed. Phenotypic response including cell morphology and production of pyoverdine, pyocyanin, and rhamnolipid were assessed. Proteomic responses were evaluated using comparative iTRAQ labeling LC-MS/MS to figure out differentially expressed proteins (DEPs).</p