A Simple Design Algorithm For Synthesis Of Multilevel Combinational Networks

An algorithm is presented for the synthesis of combinational networks with a constrained arrangement of ANDS, ORS, NANDS, NORS, and inverters. The algorithm is easily presented to students in an introductory logic design course and has considerable application in modern practical logic design. Many texts available for a first course in logic design give very limited practical guidance for synthesis of networks under constraints outlined here. It is suggested that the algorithm presented here be furnished as supplementary material in the introductory course. Copyright © 1968 by The Institute of Electrical and Electronics Engineers, Inc

A State Assignment Procedure For Asynchronous Sequential Circuits

This paper presents a new procedure for constructing nonuniversal shared-row internal state assignments for asynchronous sequential circuits. The method consists basically of establishing an initial code with the minimum number of variables required to dis. © 1971, IEEE. All rights reserved

A Simplification Heuristic For Large Flow Tables

Flow tables specifying large asynchronous sequential circuits often contain more internal states than are required to specify desired circuit behavior. Known minimization techniques appear unsuited for reduction of such large (rows X columns \u3e 250) flow tables, because of excessive computation and intermediate data requirements for problems of this size. The algorithm described here is intended to rapidly produce a simplified-but in general non-minimal-flow table. It is most economical when applied to extremely large tables and was devised primarily for automated design applications. The procedure has been programmed in PL/1 and has been incorporated into an asynchronous sequential circuit design automation system developed at the University of Missouri-Rolla. Typical flow table simplification times obtained using the program are cited. In one test re-duction of a 217 row x 8 column table to 39x8 required about 2.6 minutes (the minimum table in this case was known to be 23x8)

An Asynchronous Circuit Design Language (ACDL)

This correspondence describes a special purpose Asynchronous Circuit Design Language (ACDL) for specifying the terminal behavior of asynchronous sequential circuits. The language is a valuable tool for formalizing and documenting asynchronous designs, as well as providing a user interface to a completely automated synthesis system. The language includes many special features which permit quick and precise specification of terminal behavior and is best suited for problems that are currently being described informally by word statements. Copyright © 1974 by The Institute of Electrical and Electronics Engineers, Inc

State Assignment Selection In Asynchronous Sequential Circuits

Methods already exist for the construction of critical race-free assignments for asynchronous sequential circuits. Some of these methods permit the construction of many assignments for the same flow table. The algorithm presented here consists of two easy to apply tests which select that critical race-free assignment most likely to produce a set of simple next-state equations. The algorithm has been programmed. Copyright © 1970 by The Institute of Electrical and Electronics Engineers, Inc

Maximum-Distance Linear Codes

Described here is a linear code that has a maximum distance between codewords of k for a code of order 2k. Since the minimum-maximum distance is k for a code of order 2k, a class of minimum-maximum distance codes results. For an (n,k) linear code, k ≤ n ≤ k + k∣2 for k even and k ≤ n ≤ k + (k - 1)/2 for k odd. Maximum-distance codes are found useful in encoding the states of sequential circuits. © 1971, IEEE. All rights reserved

A Computer-Automated Laboratory System In A University Environment

A computer-automated laboratory system at the University of Missouri-Rolla, Rolla, which serves a wide variety of instruction and research disciplines including Geophysics, Cloud Physics, and Computer Graphics, is described. The system serves as an example for campuses which are relatively small in geographic area and with budget limitations which dictate a step-by-step evolution. The paper describes 1) the constraints and economics realized in the development of the system, 2) the characteristics of the minicomputer network, and 3) an evaluation of the system philosophy and performance. Also included is a description of diverse laboratory projects supported by the computer-automated system. © 1975, IEEE. All rights reserved

Generation Of Design Equations In Asynchronous Sequential Circuits

One step in the synthesis procedure for realizing an asynchronous sequential switching circuit is the generation of next-state and output state equations from a simplified and coded flow table description of the circuit. The usual approach for determining these equations is to first construct a state table from the coded flow table, and then construct transition and output tables. For large flow tables this can be quite a lengthy procedure. This note describes an algorithm which simplifies the synthesis procedure for normal fundamental-mode circuits by permitting the determination of these equations without explicit construction of the state table, transition table, or output table. The algorithm has been programmed in PL/1. Copyright © 1969 by The Institute of Electrical and Electronics Engineers, Inc