DRC 2 : Dynamically Reconfigurable Computing Circuit based on Memory Architecture

International audienceThis paper presents a novel energy-efficient and Dynamically Reconfigurable Computing Circuit (DRC²) concept based on memory architecture for data-intensive (imaging, …) and secure (cryptography, …) applications. The proposed computing circuit is based on a 10-Transistor (10T) 3-Port SRAM bitcell array driven by a peripheral circuitry enabling all basic operations that can be traditionally performed by an ALU. As a result, logic and arithmetic operations can be entirely executed within the memory unit leading to a significant reduction in power consumption related to the data transfer between memories and computing units. Moreover, the proposed computing circuit can perform extremely-parallel operations enabling the processing of large volume of data. A test case based on image processing application and using the saturating increment function is analytically modeled to compare conventional and DRC²-based approaches. It is demonstrated that DRC²-based approach provides a reduction of clock cycle number of up to 2x. Finally, potential applications and must-be-considered changes at different design levels are discussed

Special issue on Monolithic 3D: Technology, Design and Computing Systems Applications Perspectives

International audienceScope and PurposeOver the last 50 years, Computing Systems have successfully surfed the Moore’s law wave. Today, we observe a clear stagnation in this miniaturization race while a new generation of applications (such as Artificial Intelligence) are producing unprecedented amounts of raw data. To overcome this major challenge, new technologies aiming at revising classical Computing Architecture that are continuously moving data from the processing unit to memory are essential. Monolithic-3D technology (M3D) has the potential to improve the energy efficiency of new computing architectures. Indeed, thanks to its nano-scale Monolithic Inter Tier Via that is 100x smaller than state of the art Through Silicon Vias, M3D opens the door for new computing systems immersed in memory.Currently, there is much effort spent on M3D technology development and system-level design. Yet, numerous challenges remain. For example, the development of “cold process” to monolithically fabricate a reliable device on top of another one. Another challenge is on the understanding of the physical issues (electro-thermal) and design of energy efficient and reliable M3D systems. Ultimately, CAD tools for planar technology must be adapted for M3D to enable new computing architectures for large on-chip memory bandwidth. This special issue aims at addressing these problems to speed up the emergence of High Energy Efficient Computing Systems

Cell-on-Buffer: New design approach for high-performance and low-power monolithic 3D integrated circuits

International audienceMonolithic 3D Integration technology (M3D) provides high density vertical interconnects allowing new design approaches such as Cell-on-Cell (gate level approach) and NMOS-on-PMOS (transistor level approach). This work proposes a 3D Cell-on-Buffer (3DCoB) design approach by separating the logical functioning stage of a gate from its driving stage, then vertically stacking them. The proposed 3DCoB approach demonstrates better performances compared to the 2D implementation and the conventional 3D approaches. A Multi-VDD low-power technique is applied to 3DCoB cells (i.e. a different power supply for each tier). The multi-VDD 3DCoB technique provides total power reduction with limited performances degradation compared to the single-VDD 3DCoB approach. 3DCoB with single- and Multi- VDD techniques are applied on a set of benchmark designs in 28 nm-FDSOI technology using conventional sign-off place and route flow. Implementation results show up to 35% increment in performance and up to 21.8% reduction in the total power compared to 2D designs

M3D-ADTCO: Monolithic 3D architecture, design and technology co-optimization for high energy efficient 3D IC

International audienceMonolithic 3D (M3D) stands now as the ultimate technology to side step Moore's Law stagnation. Due to its nanoscale Monolithic Inter-tier Via (MIV), M3D enables an ultrahigh density interconnect between Logic and Memory that is required in the field of highly energy efficient 3D integrated circuits (3D-ICs) designed for new abundant data computing systems. At design level, M3D still suffers from a lack of commercial tools, especially for Place and Route, precluding the capability to provide signoff M3D GDS. In this paper, we introduce M3D-ADTCO, an architecture, design and technology co-optimization platform aimed at providing signoff M3D GDS. It relies on a M3D Process Design Kit and the use of a commercial Place and Route tool. We demonstrate an area reduction of 23.61 % at iso performance and power compared to a 2D RISC-V micro-controller based System on Chip (SoC) while creating space to increase (2x) the RISC-V instruction memory

Compact Interconnect Approach for Networks of Neural Cliques Using 3D Technology

International audienceThanks to their brain-like properties, neural networks outperform traditional algorithms in certain group of applications. However, since they are wire-dominated systems, their hardware implementation poses numerous challenges as high latency and energy consumption. The recent technological improvements allow for stacking few dies one on another and designing 3D electronic circuits. This creates opportunities for 3D efficient implementations of neural networks targeting high-performance applications. This work explores the gains of 3D technology for neural networks relying on neural cliques. A general study shows up to 55% reduction in terms of total interconnect length and interconnect power consumption, and 74% reduction of the maximal interconnect delay. The proposed approach is validated with a power management applicative test-case. We demonstrate that, in this scenario, the 3D architecture reduces interconnect length and power by 35% and the maximal delay by 57%, compared to 2D

A TCXO-less 100Hz-minimum-bandwidth transceiver for ultra-narrow-band sub-GHz IoT cellular networks

International audienceUltra-narrow-band (UNB) signaling is an enabling technology for low-power wide-area (LPWA) networks for the “Internet-of-Things”. Indeed, UNB signaling, based on spectrally efficient modulations such as DBPSK, simultaneously optimizes network capacity while maximizing the communication link budget. However, UNB signaling poses many technical challenges. In the receiver, carrier frequency offsets (CFO) can shift the desired signal from the expected channel. In the transmitter, the difficulty resides in generating the modulated signal with the required spectral purity. This work presents an 850-to-920 MHz RF transceiver dedicated to UNB communication systems employing the DBPSK/GFSK modulations. The receiver is resistant to CFO offsets and drifts of ±75Hz (i.e. 150% of the 100Hz channel) and 35Hz/s, respectively, with only 1dB sensitivity loss, thus allowing the circuit to function without a TCXO. In DBPSK 100b/s transmission mode, an error vector magnitude (EVM) better than 5% is measured for output powers up to 10dBm

ADVANCED 3D DESIGN AND TECHNOLOGIES FOR 3-LAYER SMART IMAGER

International audienceCMOS Imagers have adopted 3D integration using Back-Side Illumination (BSI) technology, with 2 CMOS layers assembled using Wafer-to-Wafer and advanced Hybrid Bonding technology. Targeting innovative AI and Machine Learning application, for offering AI processing at the edge within the image sensor itself, this paper presents some new 3D design and technology solutions in order to build a 3-layer Smart Imager. The hybrid bonding technology for assembly of multi wafers with a capability below 1 µm pitch is shown as well as Through Silicon Via (TSV) of 2 µm pitch compatible with hybrid bonding. To offer Design Technology Co-Optimization (DTCO) capabilities, a Place & Route methodology is proposed with the associated PDKIT to benefit of fine pitch interconnect

Advanced 3D technologies and architectures for 3D Smart Image Sensors

International audienceImage Sensors will get more and more pervasive into their environment. In the context of Automotive and IoT, low cost image sensors, with high quality pixels, will embed more and more smart functions, such as the regular low level image processing but also object recognition, movement detection, light detection, etc. 3D technology is a key enabler technology to integrate into a single device the pixel layer and associated acquisition layer, but also the smart computing features and the required amount of memory to process all the acquired data. More computing and memory within the 3D Smart Image Sensors will bring new features and reduce the overall system power consumption. Advanced 3D technology with ultra-fine pitch vertical interconnect density will pave the way towards new architectures for 3D Smart Image Sensors, allowing local vertical communication between pixels, and the associated computing and memory structures. The presentation will give an overview of recent 3D technologies solutions, such as Hybrid Bonding technology and the Monolithic 3D CoolCube™ technology, with respective 3D interconnect pitch in the order of 1 μm and l00nm. Recent 3D Image Sensors will be presented, showing the capability of 3D technology to implement fine grain pixel acquisition and processing with ultra-high speed image acquisition and tile-based processing. As further perspectives, multi-layer 3D image sensor based on events and spiking will reduce power consumption with new detection and learning processing capabilities

IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management

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A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm 2 Inter-Chiplet Interconnects and 156mW/mm 2 @ 82%-Peak-Efficiency DC-DC Converters

International audienceIn the context of high performance computing, the integration of more computing capabilities with generic cores or dedicated accelerators for AI application is raising more and more challenges. Due to the increasing costs of advanced nodes and the difficulties of shrinking analog and circuit IOs, alternative architecture solutions to single die are becoming mainstream. Chiplet-based systems using 3D technologies enable modular and scalable architecture and technology partitioning. Nevertheless, there are still limitations due to chiplet integration on passive interposers – silicon or organic. In this paper we present the first CMOS active interposer, integrating i) power management without any external components, ii) distributed interconnects enabling any chiplet-to-chiplet communication, iii) system infrastructure, Design-for-Test, and circuit IOs. The INTACT circuit prototype integrates 6 chiplets in FDSOI 28nm technology, which are 3D-stacked onto this active interposer in 65nm process, offering a total of 96 computing cores. Full scalability of the computing system is achieved using an innovative scalable cache coherent memory hierarchy, enabled by distributed Network-on-Chips, with 3Tbit/s/mm2 high bandwidth 3D-plug interfaces using 20μm pitch micro-bumps, 0.6ns/mm low latency asynchronous interconnects, while the 6 chiplets are locally power-supplied with 156mW/mm2@ 82%-peak-efficiency DC-DC converters through the active interposer. Thermal dissipation is studied showing the feasibility of such approach