Selbstadaptierende Hardware/Software-rekonfigurierbare Netzwerke - Konzepte, Methoden und Implementierung

Embedded networks are systems that consist of communicating nodes specialized for certain purposes. Typically, these systems underly constraints such as fault-tolerance, availability but also flexibility. This thesis presents a novel framework for increasing fault-tolerance and flexibility by separating functionality from structure. Based on Field-Programmable Gate Arrays (FPGAs) in combination with a CPU, the presented methodology allows that tasks implemented in hardware or software can migrate from one node to another in case of a node defect. If not enough hardware/software resources are available the online methodology allows that functionality can change its implementation style at runtime, i.e. a task can either run in hardware or software respectively.Eingebettete Netzwerke sind Systeme, die aus kommunizierenden Knoten bestehen, welche für bestimmte Aufgaben spezialisiert sind. Typischerweise unterliegen diese Systeme Randbedingungen wie Fehlertoleranz, Verfügbarkeit aber auch Flexibilität. Aus diesem Grund stellt diese Arbeit eine Methodik vor, welche die Fehlertoleranz und Flexibilität durch eine Trennung der Funktionalität von der Struktur steigert. Basierend auf einer Kombination aus Field-Programmable Gate Array (FPGAs) und CPU ermöglicht die vorgestellte Methodik, dass Software- wie auch Hardware-Tasks im Fall eines Ressourcedefekts zwischen Knoten migrieren können. Wenn nicht ausreichend Hardware/Software-Ressourcen vorhanden sind, kann zur Laufzeit die Implementierungsart geändert werden, Tasks können also entweder auf Hardware- oder Software-Ressourcen laufen

Predictive maintenance with a minimum of sensors using pneumatic clamps as an example

In standard pneumatics, the available signals for data analytics are very limited. As a rule, no continuous status information is available. Usually only the reaching of the end position is indicated - by means of a digital signal of a proximity sensor. This paper examines whether these limited data can be used to derive usable and useful information for predictive maintenance. Pneumatic clamps in bodyin- white construction were chosen as application example. The paper describes a continuous run to investigate the basic feasibility of predictibility. In the following chapters, possibilities for error classification are discussed. Finally, the implementation of the findings in a field test is described

Distributed HW/SW-Partitioning for Embedded Reconfigurable Networks

In this paper, we propose a distributed online HW/SWpartitioning strategy for increasing fault tolerance in HW/SW-reconfigurable networked systems

Modeling and design of fault-tolerant and self-adaptive reconfigurable networked embedded systems

Automotive, avionic, or body-area networks are systems that consist of several communicating control units specialized for certain purposes. Typically, different constraints regarding fault tolerance, availability and also flexibility are imposed on these systems. In this article, we will present a novel framework for increasing fault tolerance and flexibility by solving the problem of hardware/software codesign online. Based on field-programmable gate arrays (FPGAs) in combination with CPUs, we allow migrating tasks implemented in hardware or software from one node to another. Moreover, if not enough hardware/software resources are available, the migration of functionality from hardware to software or vice versa is provided. Supporting such flexibility through services integrated in a distributed operating system for networked embedded systems is a substantial step towards self-adaptive systems. Beside the formal definition of methods and concepts, we describe in detail a first implementation of a reconfigurable networked embedded system running automotive applications. Copyright © 2006 Thilo Streichert et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. 1

Modeling and Synthesis of Hardware-Software Morphing

In state of the art hardware-software-co-design flows for FPGA based systems, the hardware-software partitioning problem is solved offline, thus, omitting the great flexibility provided through partial runtime reconfiguration. The decision which functions are best suitable to be implemented in hardware or software, is typically taken with respect to the expected worst case computational demands and certain objectives like power consumption, throughput or cost. However, if these parameters change at runtime, e.g., due to environmental changes, traditional designed systems lack to adapt to the new conditions, because the hardware-software partitioning is static. In this paper we will systematically present a new methodology that allows to change the implementation style of tasks at runtime by hardware-software morphing. Based on a formal model, we will demonstrate, how morphing can be performed without loosing internal states. Moreover, we will present results from applying our methodology to a 16-tap FIR filter

Dynamic Task Binding for Hardware/Software Reconfigurable Networks

In this paper, a new methodology for tolerating link as well as node defects in self-adaptive reconfigurable networks will be presented. Currently, networked embedded systems need a certain level of redundancy for each node and link in order to tolerate defects and failures in a network. Due to monetary constraints as well as space and power limitations, the replication of each node and link is not an option in most embedded systems. Therefore, we will present a hardware/software partitioning algorithm for reconfigurable networks that optimizes the task binding onto resources at runtime such that node/link defects can be handled and data traffic on links between computational nodes will be minimized. This paper presents a new hardware/software partitioning algorithm, an experimental evaluation and for demonstrating the realizability, an implementation on a network of FPGA-based boards

Formal Analysis of the Startup Delay of SOME/IP Service Discovery

An automotive network needs to start up within the millisecond range. This includes the physical startup, the software boot time, and the configuration of the network. The introduction of Ethernet into the automotive industry expanded the design space drastically and is increasing the complexity of configuring every element in the network. To add more flexibility to automotive Ethernet networks, the concept of Service Discovery was migrated from consumer electronics to AUTOSAR within the SOME/IP middleware. A network is not fully functional until every client has found its service. Consequently, this time interval adds to the startup time of a network. This work presents a formal analysis model to calculate the waiting time of every client to receive the first offer from its service. The model is able to determine the worst case of a given parameter set. Based on this, a method for calculating the total startup time of a system is derived. The model is implemented in a free-to-use octave program and validated by comparing the analytical results to a timing-accurate simulation and an experimental setup. In every case the worst-case assumption holds true -- the gap between the maximum of the simulation and the presented method is less than 1.3%