Opinion, knowledge, and clinical experience with functional neurological disorders among Italian neurologists: results from an online survey

Background: Functional neurological disorders (FND) are disabling medical conditions commonly seen in neurological practice. Neurologists play an essential role in managing FND, from establishing a diagnosis to coordination of multidisciplinary team-based treatment for patients. With this study, we investigated the knowledge and the clinical experience of Italian neurologists in managing patients with FND. Methods: Members of the Italian Society of Neurology were invited via e-mail to participate in this ad hoc online survey; 492 questionnaires were returned completed. Results: The term "Functional neurological disorders" in reference to FND was used more frequently than other psychological (e.g., psychogenic or conversion), or descriptive terms (e.g., non-organic or stress-related). When speaking with patients, the respondents stated that they preferred explaining symptoms based on abnormal functioning of the nervous system than discussing mental illness and that they would refer their patient to a psychologist rather than to a psychiatrist. Few considered that physiotherapy and psychiatric interventions are useful approaches to treating FND. Some believed that patients simulate their symptoms. Conclusions: Overall, the responses suggest that knowledge about scientific advances in FND is somewhat sparse. A psychiatric-centered view of FND opens the way to an approach in which neurobiological and psychological aspects constitute essential factors of the condition. In this context, professional education could improve understanding of FND and optimize patient management

Data-driven clustering of combined Functional Motor Disorders based on the Italian registry

Functional Motor Disorders (FMDs) represent nosological entities with no clear phenotypic characterization, especially in patients with multiple (combined FMDs) motor manifestations. A data-driven approach using cluster analysis of clinical data has been proposed as an analytic method to obtain non-hierarchical unbiased classifications. The study aimed to identify clinical subtypes of combined FMDs using a data-driven approach to overcome possible limits related to "a priori" classifications and clinical overlapping

A Novel Topology of Coupled Phase-Locked Loops

This paper analyses the noise performances of coupled phase-locked loops, providing closed-form expressions for the transfer functions of the various noise sources, and presents a novel coupling topology, whose goal is the reduction of both in-band and out-of-band phase-noise. The proposed circuit consists of two, or more, standard loops coupled via an additional phase detector. It will be demonstrated that in this architecture the impact of the main PLL noise sources, the oscillator and the reference buffer, is efficiently traded with the power dissipation without resorting to lossy and area-consuming passive coupling networks. The work then shows how to derive the set of design parameters that grant the desired performance for a given case study. The entire procedure is verified by simulations

A Novel LO Phase-Shifting System Based on Digital Bang-Bang PLLs With Background Phase-Offset Correction for Integrated Phased Arrays

An LO phase-shifting system based on digi- tal fractional-N bang-bang phase-locked loops (PLLs) in the 8.5–10.0-GHz range is presented. A direct phase modulation method is leveraged to perform LO phase-shifting directly within the frequency synthesizer, leading to an inherently linear phase-shifting characteristic, even in the presence of digital-to- time converter (DTC) nonlinearities. Synchronization between fractional-N PLL cores is achieved by clocking with the same reference clock the 16 modulator driving the frequency divider of each core. The adoption of a digital phase-offset correction technique canceling out timing skews greatly simplifies the reference-clock distribution and DTC matching. A dual-core prototype is implemented in a standard 28-nm CMOS process, where each element occupies 0.23-mm2 area and dissipates 20-mW power. An arbitrary phase shift between the LO outputs can be set over the 360◦ range with a resolution of 0.7 millidegree (19 bits). The rms phase accuracy is 0.76°, and the peak-to- peak phase error is 2.1°, without requiring any linearity or gain calibration. Each LO element features a −58.7 dBc in-band fractional spur and a −70 dBc reference spur, with a jitter versus power figure-of-merit of −253.5 and −250.0 dB for integer-N and fractional-N channels, respectively. The combined outputs of the two PLL cores reach an absolute jitter integrated from 1 kHz to 100 MHz (including spurs) of 38.2 and 59.78 fs, in integer-N and near-integer fractional-N operations, respectively

10.6 A 10GHz FMCW Modulator Achieving 680MHz/μs Chirp Slope and 150kHz rms Frequency Error Based on a Digital-PLL with a Non-Uniform Piecewise-Parabolic Digital Predistortion

Improving the spatial resolution and reliability of target detection in CMOS FMCW radars is essential to facilitate the increased adoption of next generation fully autonomous driving vehicles. In this frame, digital PLLs using the two-point modulation (TPM) scheme (Fig. 10.6.1 top-left) are attractive solutions, thanks to their capability of generating fast and wide-bandwidth (BW) chirp modulations with short retrace time at low power, area, and phase noise [1–3]. Unfortunately, the non-linearity of the digitally controlled oscillator (DCO) degrades chirp linearity, generating significant spurs and triggering the detection of false targets. This issue combined with the existence of a trade-off between linearity and phase noise in the design of DCOs makes it difficult to further improve radar resolution. The piecewise-linear digital predistortion (PWL-DPD) mitigates DCO non-linearity [1, 4, 5] but has limited effectiveness in the case of non-smooth DCO tuning curves, such as that induced by the practical layout of a low-noise wide-range DCO. Substituting the DCO capacitor banks with a varactor driven by a DAC may be a solution [4, 5], but at the cost of a much larger power consumption; limited chirp slope and longer retrace time. To solve those limitations, this work introduces a non-uniform piecewise-parabolic digital predistortion (PWP-DPD), specifically designed to mitigate non-smooth DCO non-linearities. The implemented 10GHz PLL dissipates 21mW of power and achieves a phase noise of -116.5dBc/Hz at a 1MHz offset, as well as an rms frequency error below 150kHz when synthesizing sawtooth and triangular chirps at slope and bandwidth up to 680MHz/μs and 680MHz, respectively

A 66.7fs-Integrated-Jitter Fractional-N Digital PLL Based on a Resistive-Inverse-Constant-Slope DTC

Modern fractional-N PLLs used as low-jitter local oscillators for wireless systems generally adopt a digital-to-time converter (DTC) to cancel-out the quantization-error (QE) induced by dithering the modulus control of the frequency divider in feedback [1], [2], [4], [5]. Unfortunately, DTC non-linearity distorts the QE sequence fed to DTC input, thus causing significant fractional spurs at the PLL output and limiting spectral purity and jitter (Fig. 1 top). The inverse-constant-slope DTC (ICS-DTC), recently introduced in [1], has improved linearity over prior-art DTC architectures; however, this comes at the price of a larger DTC jitter, caused by the current generators (CGs) adopted in that circuit. This work introduces an 8.75-10.25GHz fractional-N digital PLL leveraging a resistor-based ICS-DTC circuit, which significantly improves phase-noise while retaining high-linearity. The implemented PLL prototype achieves 66.7fs rms jitter (including spurs), -63.8dBc fractional spur and - 108.5dBc/Hz in-band phase noise (PN) at 10kHz offset, using a 125MHz reference frequency

4.5 A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology

The quest of increasingly higher mobile uplink/downlink data-rates has recently driven the communication industry to set extremely challenging requirements on the integrated jitter of local oscillators [1]. In fractional-N PLLs, the adoption of a digital-to-time-converter (DTC) has become ubiquitous to meet performance targets, as it greatly improves integrated jitter by re-aligning the edges of the reference and the divider signals (top-left of Fig. 4.5.1) [2], [2]. Unfortunately, any DTC non-linearity converts the quantization error (QE) , driving the DTC into fractional spurs in the PLL spectrum, thus degrading the integrated jitter. Several digital techniques have been proposed to reduce the DTC non-linearity either at the cost of increasing hardware resources [3] or requiring calibration loops with long convergence times [4]. Other techniques dither the DTC control word [5], [6], spreading the spurious-tones power over a larger bandwidth, but the total jitter improvement is limited. This work introduces a fractional-spur-cancellation technique based on a multi-DTC topology with phase-shifted quantization-error sequences that allows the cancellation of the dominant fractional-spur tones and, at the same time, the reduction of the in-band phase-noise (PN). The concept is demonstrated in a 9.25GHz fractional-N DPLL, which achieves a total rms jitter of 77.1fs (including fractional spurs) for near-integer channels and an in-band fractional spur of −60.3dBc

4.3 A 76.7fs-lntegrated-Jitter and −71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering

Ultra-low-jitter and high-spectral-purity frequency synthesizers are key building blocks for high-performance wireless transceivers and $\text{FMCW}$ radars. A bang-bang $\text{PLL} (\text{BBPLL}$ ) is an attractive solution thanks to its small footprint and low power consumption; however, its operation in the $\text{fractional-N}$ mode is hindered by the large quantization error $(\text{Q-error})$ I caused by the non-integer frequency multiplication saturating the narrow input range of the bang-bang phase detector $(\text{BBPD})$ . A digital-to-time converter $(\text{DTC})$ is typically used to cancel the $\text{Q-error}$ in time domain [1] (Fig. 4.3.1 top-left). Unfortunately, the $\text{DTC}$ non-linearity can generate significant fractional spurs, thus corrupting the $\text{PLL}$ spectral purity and integrated jitter. Solutions to this problem rely on either improving the $\text{DTC}$ linearity or adopting a suitable randomization of the $\text{Q-error}$ sequence to generate lower spurs in the presence of the $\text{DTC}$ non-linearity. The constant slope $\text{DTC} (\text{CS-DTC})$ achieves superior linearity among $\text{DTC}$ architectures [2], even if further improvements are limited by the voltage sensitivity of current generators $(\text{CGs})$ and parasitic capacitances as well as by the non-linearity of the digital-to-analog converter $(\text{DAC})$ adopted in the circuit. On the other hand, those randomization techniques to reduce spurs typically require a larger $\text{Q-error}$ range [3], [4] that increases $\text{PLL jitter}$ for two reasons: the higher quantization-noise power and the larger random jitter induced by the wider range needed for the $\text{DTC}$ . This work introduces a $9.25-\text{to}-10.5\text{GHz} \text{fractional-N BBPLL}$ achieving $-71.9\text{dBc}$ fractional spur and a total rms jitter (including spurs) of $76.7\text{fs}$ at near-integer channels leveraging: $(\mathrm{i})$ a $\text{DTC}$ architecture (denoted as $inverse constant-slope DTC)$ I overcoming the $\text{CS-DTC}$ limitations and $(\text{ii})$ a $\text{Q-error}$ randomization technique (denoted as $FCW$ subtractive dithering), which keeps the $\mathrm{Q}- \text{error}$ range constant thus not degrading $\text{PLL jitter}

10.1 An 8.75GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-Slope DTC Achieving 57.3fsrms Integrated Jitter and −252.4dB FoM

Advanced wireless transceivers exploit high-order modulation schemes to increase data-rates and call for high-spectral-purity frequency synthesizers. To serve this purpose, a fractional-N PLL that removes the time quantization error between the reference and divider signals through a digital-to-time converter (DTC) can be used, a technique which is now widespread among high-performance PLLs (Fig. 10.1.1 top) [1]. However, non-idealities, such as the DTC non-linearity and noise, degrade spectral purity, appearing either as fractional spurs or higher in-band phase noise in the PLL spectrum. Thanks to its simplicity and superior power-jitter trade-off, a variable-slope DTC (VS-DTC) is one of the most used DTC topologies [2–5]. Unfortunately, its linearity is affected by the slope-dependent propagation delay, T2, of the output stage. This causes an integral non-linearity (DTCINL) with a downward concavity (Fig. 10.1.1 bottom-left) [6]. The DTCINL is typically improved by adding a fixed capacitance, CFIX, at the output of the first stage, which reduces the voltage slope variation [4]. This method essentially trades a better DTC linearity for higher DTC phase noise (DTCPN) and power consumption. A similar trade-off exists in an alternative DTC architecture, i.e., the constant-slope DTC, that achieves better linearity by keeping a constant voltage slope at the input of the output stage [6] at the cost of a worse power-jitter product [5]. This work introduces a DTC topology, denoted as reverse-concavity variable-slope DTC (RCVS-DTC), which breaks the power-jitter-vs-linearity trade-off. The concept is demonstrated in an 8.75GHz fractional-N digital PLL achieving 57.3fs integrated jitter, a fractional spur of −63.4dBc, and a −252.4dB FoM