What constitutes a nanoswitch? A Perspective

Progress in the last two decades has effectively integrated spintronics and nanomagnetics into a single field, creating a new class of spin-based devices that are now being used both to Read (R) information from magnets and to Write (W) information onto magnets. Many other new phenomena are being investigated for nano-electronic memory as described in Part II of this book. It seems natural to ask whether these advances in memory devices could also translate into a new class of logic devices. What makes logic devices different from memory is the need for one device to drive another and this calls for gain, directionality and input-output isolation as exemplified by the transistor. With this in mind we will try to present our perspective on how W and R devices in general, spintronic or otherwise, could be integrated into transistor-like switches that can be interconnected to build complex circuits without external amplifiers or clocks. We will argue that the most common switch used to implement digital logic based on complementary metal oxide semiconductor (CMOS) transistors can be viewed as an integrated W-R unit having an input-output asymmetry that give it gain and directionality. Such a viewpoint is not intended to provide any insight into the operation of CMOS switches, but rather as an aid to understanding how W and R units based on spins and magnets can be combined to build transistor-like switches. Next we will discuss the standard W and R units used for magnetic memory devices and present one way to integrate them into a single unit with the input electrically isolated from the output. But we argue that this integrated W-R unit would not provide the key property of gain. We will then show that the recently discovered giant spin Hall effect could be used to construct a W-R unit with gain and suggest other possibilities for spin switches with gain.Comment: 27 pages. To appear in Emerging Nanoelectronic Devices, Editors: An Chen, James Hutchby, Victor Zhirnov and George Bourianoff, John Wiley & Sons (to be published

Direct tunneling through high-κ\kappa amorphous HfO2_2: effects of chemical modification

We report first principles modeling of quantum tunneling through amorphous HfO$_2$ dielectric layer of metal-oxide-semiconductor (MOS) nanostructures in the form of n-Si/HfO$_2$/Al. In particular we predict that chemically modifying the amorphous HfO$_2$ barrier by doping N and Al atoms in the middle region - far from the two interfaces of the MOS structure, can reduce the gate-to-channel tunnel leakage by more than one order of magnitude. Several other types of modification are found to enhance tunneling or induce substantial band bending in the Si, both are not desired from leakage point of view. By analyzing transmission coefficients and projected density of states, the microscopic physics of electron traversing the tunnel barrier with or without impurity atoms in the high-$\kappa$ dielectric is revealed.Comment: 5 pages, 5 figure

Shrinking limits of silicon MOSFET's: Numerical study of 10-nm-scale devices

We have performed numerical modeling of dual-gate ballistic n-MOSFET's with channel length of the order of 10 nm, including the effects of quantum tunneling along the channel and through the gate oxide. Our analysis includes a self-consistent solution of the full (two-dimensional) electrostatic problem, with account of electric field penetration into the heavily-doped electrodes. The results show that transistors with channel length as small as 8 nm can exhibit either a transconductance up to 4,000 mS/mm or gate modulation of current by more than 8 orders of magnitude, depending on the gate oxide thickness. These characteristics make the devices satisfactory for logic and memory applications, respectively, though their gate threshold voltage is rather sensitive to nanometer-scale variations in the channel length.Comment: 8 pages, 10 figures. Submitted to Special Issue of Superlattices and Microstructures: Third NASA Workshop on Device Modeling, August 199

Understanding the Mechanism of Electronic Defect Suppression Enabled by Nonidealities in Atomic Layer Deposition.

Silicon germanium (SiGe) is a multifunctional material considered for quantum computing, neuromorphic devices, and CMOS transistors. However, implementation of SiGe in nanoscale electronic devices necessitates suppression of surface states dominating the electronic properties. The absence of a stable and passive surface oxide for SiGe results in the formation of charge traps at the SiGe-oxide interface induced by GeOx. In an ideal ALD process in which oxide is grown layer by layer, the GeOx formation should be prevented with selective surface oxidation (i.e., formation of an SiOx interface) by controlling the oxidant dose in the first few ALD cycles of the oxide deposition on SiGe. However, in a real ALD process, the interface evolves during the entire ALD oxide deposition due to diffusion of reactant species through the gate oxide. In this work, this diffusion process in nonideal ALD is investigated and exploited: the diffusion through the oxide during ALD is utilized to passivate the interfacial defects by employing ozone as a secondary oxidant. Periodic ozone exposure during gate oxide ALD on SiGe is shown to reduce the integrated trap density (Dit) across the band gap by nearly 1 order of magnitude in Al2O3 (<6 × 1010 cm-2) and in HfO2 (<3.9 × 1011 cm-2) by forming a SiOx-rich interface on SiGe. Depletion of Ge from the interfacial layer (IL) by enhancement of volatile GeOx formation and consequent desorption from the SiGe with ozone insertion during the ALD growth process is confirmed by electron energy loss spectroscopy (STEM-EELS) and hypothesized to be the mechanism for reduction of the interfacial defects. In this work, the nanoscale mechanism for defect suppression at the SiGe-oxide interface is demonstrated, which is engineering of diffusion species in the ALD process due to facile diffusion of reactant species in nonideal ALD

Pathogenicity locus, core genome, and accessory gene contributions to Clostridium difficile virulence

Clostridium difficile is a spore-forming anaerobic bacterium that causes colitis in patients with disrupted colonic microbiota. While some individuals are asymptomatic C. difficile carriers, symptomatic disease ranges from mild diarrhea to potentially lethal toxic megacolon. The wide disease spectrum has been attributed to the infected host’s age, underlying diseases, immune status, and microbiome composition. However, strain-specific differences in C. difficile virulence have also been implicated in determining colitis severity. Because patients infected with C. difficile are unique in terms of medical history, microbiome composition, and immune competence, determining the relative contribution of C. difficile virulence to disease severity has been challenging, and conclusions regarding the virulence of specific strains have been inconsistent. To address this, we used a mouse model to test 33 clinical C. difficile strains isolated from patients with disease severities ranging from asymptomatic carriage to severe colitis, and we determined their relative in vivo virulence in genetically identical, antibiotic-pretreated mice. We found that murine infections with C. difficile clade 2 strains (including multilocus sequence type 1/ribotype 027) were associated with higher lethality and that C. difficile strains associated with greater human disease severity caused more severe disease in mice. While toxin production was not strongly correlated with in vivo colonic pathology, the ability of C. difficile strains to grow in the presence of secondary bile acids was associated with greater disease severity. Whole-genome sequencing and identification of core and accessory genes identified a subset of accessory genes that distinguish high-virulence from lower-virulence C. difficile strains

Computational Study of Tunneling Transistor Based on Graphene Nanoribbon

Tunneling field-effect transistors (FETs) have been intensely explored recently due to its potential to address power concerns in nanoelectronics. The recently discovered graphene nanoribbon (GNR) is ideal for tunneling FETs due to its symmetric bandstructure, light effective mass, and monolayer-thin body. In this work, we examine the device physics of p-i-n GNR tunneling FETs using atomistic quantum transport simulations. The important role of the edge bond relaxation in the device characteristics is identified. The device, however, has ambipolar I-V characteristics, which are not preferred for digital electronics applications. We suggest that using either an asymmetric source-drain doping or a properly designed gate underlap can effectively suppress the ambipolar I-V. A subthreshold slope of 14mV/dec and a significantly improved on-off ratio can be obtained by the p-i-n GNR tunneling FETs

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Eesti Arst 2024; 103(11):57

Web-Based Single-Player Project Simulation Game

Selles lõpputöös tehakse tarkvaraarenduse simulatsioonimudel ja selle rakendamine veebipõhise üksikmängija simulatsioonimängu osana.The goal of this thesis is creating a simulation model for software development and implementing it as a part of a web based single-player simulation gam