Synthesis Characterization And Photopolymerization Of Novel Phosphonated Materials

New phosphonated cross-linked materials were synthesized from telomers obtained by reaction between 10-undecenol and dialkyl hydrogenphosphonates. Telomers were then converted to materials resins by methacrylation reactions. Finally, photopolymerization of the different materials synthesized was achieved and influence of the nature of the phosphonate group (diester, monoacid and diacid) was also evaluated.New phosphonated cross-linked materials were synthesized from telomers obtained by reaction between 10-undecenol and dialkyl hydrogenphosphonates. Telomers were then converted to materials resins by methacrylation reactions. Finally, photopolymerization of the different materials synthesized was achieved and influence of the nature of the phosphonate group (diester, monoacid and diacid) was also evaluated

Applications of Computation-In-Memory Architectures based on Memristive Devices

Today's computing architectures and device technologies are unable to meet the increasingly stringent demands on energy and performance posed by emerging applications. Therefore, alternative computing architectures are being explored that leverage novel post-CMOS device technologies. One of these is a Computation-in-Memory architecture based on memristive devices. This paper describes the concept of such an architecture and shows different applications that could significantly benefit from it. For each application, the algorithm, the architecture, the primitive operations, and the potential benefits are presented. The applications cover the domains of data analytics, signal processing, and machine learning

A two minute liquid based sample preparation for rapid SARS-CoV2 real-time PCR screening: a multicentre evaluation

Background: Apart from major health concerns associated to the SARS-coronavirus-2 (SARS-CoV-2) pandemic, also the diagnostic workflow encountered serious problems. Limited availability of kit components, buffers and even plastics has resulted in suboptimal testing procedures worldwide. Alternative workflows have been implemented to overcome these difficulties. Recently a liquid based sample prep has been launched as solution to overcome limitations in relation to nucleic acid extraction.Objective: Multicenter evaluation of the QlAprep& Viral RNA UM kit (QIA P&A) for rapid sample preparation and real-time PCR detection of SARS-CoV-2 in comparison to standardized laboratory testing methods.Study design: Selected samples of the routine diagnostic workflow at Clinical Microbiology Laboratories of four Dutch hospitals have been subjected to the rapid QIA P&A protocol and the results have been compared to routine diagnostic data.Results: Combining results of manual and automated procedures, a total of 377 clinical samples of which 202 had been tested positive with a wide range of C-T values, showed almost complete concordance in the QIA P&A assay for samples up to C-T values of 33 with one exception of C-T 31. Prospectively 60 samples were tested and also showed 100 % concordance with 5 positives. The method has been automated by two centres.Conclusions: Despite an input of only 8 mu L of clinical sample, the QIA P&A kit showed good performance for sample preparation and amplification of SARS-CoV-2 and can contribute as a rapid molecular testing strategy in managing the CoV-2 pandemic.Molecular basis of virus replication, viral pathogenesis and antiviral strategie

Using Drugs to Probe the Variability of Trans-Epithelial Airway Resistance

BACKGROUND:Precision medicine aims to combat the variability of the therapeutic response to a given medicine by delivering the right medicine to the right patient. However, the application of precision medicine is predicated on a prior quantitation of the variance of the reference range of normality. Airway pathophysiology provides a good example due to a very variable first line of defence against airborne assault. Humans differ in their susceptibility to inhaled pollutants and pathogens in part due to the magnitude of trans-epithelial resistance that determines the degree of epithelial penetration to the submucosal space. This initial 'set-point' may drive a sentinel event in airway disease pathogenesis. Epithelia differentiated in vitro from airway biopsies are commonly used to model trans-epithelial resistance but the 'reference range of normality' remains problematic. We investigated the range of electrophysiological characteristics of human airway epithelia grown at air-liquid interface in vitro from healthy volunteers focusing on the inter- and intra-subject variability both at baseline and after sequential exposure to drugs modulating ion transport. METHODOLOGY/PRINCIPAL FINDINGS:Brushed nasal airway epithelial cells were differentiated at air-liquid interface generating 137 pseudostratified ciliated epithelia from 18 donors. A positively-skewed baseline range exists for trans-epithelial resistance (Min/Max: 309/2963 Ω·cm2), trans-epithelial voltage (-62.3/-1.8 mV) and calculated equivalent current (-125.0/-3.2 μA/cm2; all non-normal, P<0.001). A minority of healthy humans manifest a dramatic amiloride sensitivity to voltage and trans-epithelial resistance that is further discriminated by prior modulation of cAMP-stimulated chloride transport. CONCLUSIONS/SIGNIFICANCE:Healthy epithelia show log-order differences in their ion transport characteristics, likely reflective of their initial set-points of basal trans-epithelial resistance and sodium transport. Our data may guide the choice of the background set point in subjects with airway diseases and frame the reference range for the future delivery of precision airway medicine

Yield and Cost Analysis or 3D Stacked ICs

3D stacking is an emerging technology promising many benefits such as low latency between stacked dies, reduced power consumption, high bandwidth communication, improved form factor and package volume density, heterogeneous integration, and low-cost manufacturing. However, it requires modification of existing methods and/or introduction of new ones with respect to design, manufacturing, and testing in order to facilitate production. In this thesis three challenges are addressed: one related to manufacturing (i.e., yield improvement) and two related to testing (i.e., cost modeling and interconnect testing). Yield improvement - We propose two yield improvement schemes applicable for 3D Stacked-ICs (3D-SICs) with similar die sizes (such as memories and FPGAs): wafer matching and layer redundancy. Wafer matching is based on algorithms that select wafers with identical or similar fault maps for stacking to boost the compound yield. Our algorithms outperform yield-wise previously proposed schemes, and more importantly reduce memory and time complexity significantly. On the other hand, redundancy in 3D memories makes use not only of conventional spare rows and columns, but also of the third dimension to access either spare dies (layer redundancy) or spare cells (inter-layer redundancy). Layer redundancy showed to be effective from a yield point of view, but may seriously affect die area and cost. Inter-layer redundancy realizes even higher yield improvements; however, it requires through-silicon vias (TSVs) to scale down with one order of magnitude for area-efficient implementations. Cost Modeling - Selecting an appropriate and efficient test flow for 2.5D/3D SICs is crucial for overall cost optimization. In addition, diverse products and applications require different quality levels resulting in different test flows; these flows may require different design-for-test (DfT) features, which need to be incorporated in the various dies during an early design stage. Therefore, an appropriate cost model used to evaluate test flows with their associated DfT, while taking into account yields and die production costs, is of great importance. A proper cost modeling tool for 2.5D/3D stacked ICs is developed; the tool is referred to as 3D-COSTAR. It considers all costs involved in the whole production chain, including design, manufacturing, test, packaging, and logistics, e.g., related to shipping wafers between a foundry and a test house. 3D-COSTAR provides the estimated overall cost for 2.5D/3D-SICs and its cost breakdown for a given input parameter set, such as test flows, die yield, stack yield etc. The crucial importance of 3D-COSTAR is demonstrated by analyzing trade-offs of different complex optimization test problems such as (a) the impact of test coverage of the pre-bond silicon interposer test, (b) the impact of pre-bond testing of active dies using either dedicated probe-pads or micro-bumps, (c) the impact of mid-bond testing and logistics, and (d) the impact of different test flows on the test escapes. Interconnect Testing - A potential application of 3D-SICs is stacking of memory on logic. However, testing the TSV interconnects between such dies is challenging, as the memory and the logic die typically come from different manufacturers. Currently, proposed solutions fail to address dynamic and time-critical faults. In addition, memory vendors have in the past not been in favor to put additional DfT structures such as IEEE 1149.1 for interconnect testing on their memory devices. We propose a new Memory-Based Interconnect Test (MBIT) approach for 3D stacked memories. Our test patterns are applied by using read and write instructions to the memory and are validated by a case study where a 3D memory is assumed to be stacked on a MIPS64 processor. The main benefits of the MBIT approach include zero area overhead, detection of both static and dynamic faults, at-speed testing, flexibility, extremely short test time, and interconnect fault diagnosis.Software and Computer TechnologyElectrical Engineering, Mathematics and Computer Scienc

A hardware Accelerator for the OpenFOAM Sparse Matrix-Vector Product

One of the key kernels in scientific applications is the Sparse Matrix Vector Multiplication (SMVM). Profiling OpenFOAM, a sophisticated scientific Computational Fluid Dynamics tool, proved the SMVM to be its most computational intensive kernel. A traditional way to solve such computationally intensive problems in scientific applications is to employ supercomputing power. This approach, however, provides performance efficiency at a high hardware cost. Another approach for high performance scientific computing is based on reconfigurable hardware. Recently, it is becoming more popular due to the increasing On-Chip memory, bandwidth and abundant reasonable cheaper hardware resources. The SGI Reconfigurable Application Specific Computing (RASC) library combines both approaches as it couples traditional supercomputer nodes with reconfigurable hardware. It supports the execution of computational intensive kernels on Customized Computing Units (CCU) in Field Programmable Gate Arrays (FPGA). This thesis presents the architectural design and implementation of the SMVM product for the OpenFOAM toolbox on an FPGA-enabled supercomputer. The SMVM is targeted to be a Custom Computing Unit (CCU) within the RASC machine. The proposed CCU comprises multiple Processing Elements (PE) for IEEE-754 compliant floating point double precision data. Accurate equations are developed that describe the relation between the number of PEs and the available bandwidth. With two PEs and an input bandwidth of 4.8 GB/s the hardware unit can outperform execution in pure software. Simulations suggest speedups between 2.7 and 7.3 for the SMVM kernel considering four PEs. The performance increase at the kernel level is nearly linear to the number of available PEs. The SMVM kernel has been synthesized and verified for the Virtex-4 LX200 FPGA and a hardware counter is integrated in the design to obtain the accurate performance results per CCU. Although the synthesis tool reports higher frequencies, the design has been routed and executed on the Altix 450 machine at 100 MHz. Based on our experimental results we can safely conclude that the proposed approach, using FPGAs as accelerator, has potential for application speedup for the SMVM kernel against traditional supercomputing approaches.Computer EngineeringElectrical Engineering, Mathematics and Computer Scienc

Cost Modeling for 2.5D and 3D Stacked ICs

This chapter discusses cost modeling for 2.5D/3D‐stacked integrated circuits (2.5D/3D‐SICs) and presents a tool that considers all costs involved in the whole production chain, including design, manufacturing, test, packaging, and logistics. The tool provides the estimated overall cost for 2.5D/3D‐SICs and its cost breakdown for a given input parameter set consisting of test flows, die yield, stack yield, etc. The chapter defines test flows and highlights the importance of testing. In order to determine the most cost‐effective test flow, test requirements should be specified. However, taking only the test cost into consideration is not sufficient to provide a fair evaluation and/or comparison; a test flow does not only impact test cost but also design and manufacturing cost. The chapter defines and classifies the different costs involved in designing and manufacturing 2.5D/3D‐SICs. It also presents the 3D‐COSTAR cost model. It shows the crucial importance of 3D‐COSTAR by analyzing trade‐offs for several test optimization problems