15 research outputs found

    Generating constrained length personalized bicycle tours

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    In the context of recreational routing, the problem of finding a route which starts and ends in the same location (while achieving a length between specified upper and lower boundaries) is a common task, especially for tourists or cyclists who want to exercise. The topic of finding a tour between a specified starting and ending location while minimizing one or multiple criteria is well covered in literature. In contrast to this, the route planning task in which a pleasant tour with length between a maximum and a minimum boundary needs to be found is relatively underexplored. In this paper, we provide a formal definition of this problem, taking into account the existing literature on which route attributes influence cyclists in their route choice. We show that the resulting problem is NP-hard and devise a branch-and-bound algorithm that is able to provide a bound on the quality of the best solution in pseudo-polynomial time. Furthermore, we also create an efficient heuristic to tackle the problem and we compare the quality of the solutions that are generated by the heuristic with the bounds provided by the branch-and-bound algorithm. Also, we thoroughly discuss the complexity and running time of the heuristic

    A General, Fault tolerant, Adaptive, Deadlock-free Routing Protocol for Network-on-chip

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    The paper presents a topology-agnostic greedy protocol for network-on-chip routing. The proposed routing algorithm can tolerate any number of permanent faults, and is proven to be deadlock-free. We introduce a specialized variant of the algorithm, which is optimized for 2D mesh networks, both flat and wireless. The adaptiveness and minimality of several variants this algorithm are analyzed through graph-based simulations.Comment: Presented at 11th International Workshop on Network on Chip Architectures (NoCArc 2018

    A General, Fault tolerant, Adaptive, Deadlock-free Routing Protocol for Network-on-chip

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    The paper presents a topology-agnostic greedy protocol for network-on-chip routing. The proposed routing algorithm can tolerate any number of permanent faults, and is proven to be deadlock-free. We introduce a specialized variant of the algorithm, which is optimized for 2D mesh networks, both flat and wireless. The adaptiveness and minimality of several variants this algorithm are analyzed through graph-based simulations.Comment: Presented at 11th International Workshop on Network on Chip Architectures (NoCArc 2018

    Graph representations for programmable photonic circuits

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    We propose graph representations for reconfigurable photonic mesh circuits. Waveguide mesh circuits are abstracted into a graph to highlight the connectivity and topology. We model the optical ports as graph nodes. Performance metrics for each connection are incorporated into the edge attributes in categories such as propagation loss, crosstalk penalty, power consumption, phase accumulation, and so on. We use three types of graph representations for tunable couplers to model the flow of light and create a circuit graph representation to an example hexagonal mesh. The representation should respect the physics of waveguide circuits (e.g. directional flow of light). Of the three types, the directed graph with eight artificial nodes performs best for solving light distributions with feedback paths. This graph representation is demonstrated in four distribution cases: a single pair input-output, multi-pair inputs and outputs without collisions, a single input to multiple outputs (distribution), and multiple distributions without collisions. The programming tolerance against malfunctioning tunable elements is also demonstrated. With this circuit representation, we can reduce all these distribution cases to different graph problems and leverage a wealth of existing algorithms developed in graph theory to program the photonic mesh. Thus we provide a systematical strategy to design and program complex reconfigurable photonic circuits, especially in photonic meshes with feedback paths

    Graph Representations for Programmable Photonic Circuits

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    Learning to forget : design of experiments for line-based Bayesian optimization in dynamic environments

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    Various scientific and engineering fields rely on measurements in 2D spaces to generate a map or locate the global optimum. Traditional design of experiments methods determine the measurement locations upfront, while a sequential approach iteratively extends the design. Typically, the cost of traveling between sample locations can be ignored, for example in simulation experiments. In those cases, the experimental design is generated using a point-based method. However, if traveling towards the next sample location incurs an additional cost, line-based sampling methods are favored. In this setting, the sampling algorithm needs to generate a route of easurement locations. A common engineering problem is locating the global optimum. In certain cases, such as fire hotspot monitoring, the location of the optimum dynamically changes. In this work, an algorithm is proposed for sequentially locating dynamic optima in a line-based setting. The algorithm is evaluated on two dynamic optimization benchmark problems

    Parallel algorithms for simulating interacting carriers in nanocommunication

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    Diffusion-based molecular communication (DMC) with interacting carrier molecules allows exploring a variety of new communication paradigms. Simulating these interactions on a network scale is however hard from an analytic point of view, and continuous detection of which couples of particles may interact is a computationally expensive task. This work proposes different algorithms that allow detecting which particles are interacting. Hierarchical grid based approaches are explored and designed to maximally exploit the parallelism offered by multiple-graphics processing units (multi-GPU) systems. An implementation of the proposed algorithm is compared to some of our previous work in this domain and to a state-of-the-art collision detection library and nanosimulator. Performance tests indicate a speedup of up to a factor 100 compared to the collision detection algorithm implemented in the nanosimulator, and a factor 77 relative to the collision detection library. (C) 2019 Elsevier B.V. All rights reserved
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