A High Frequency (HF) Inductive Power Transfer Circuit for High Temperature Applications Using SiC Schottky Diodes

Wireless sensors placed in high temperature environments, such as aircraft engines, are desirable to reduce the mass and complexity of routing wires. While communication with the sensors is straight forward, providing power wirelessly is still a challenge. This paper introduces an inductive wireless power transfer circuit incorporating SiC Schottky diodes and its operation from room temperature (25 C) to 500 C

Demonstration of 4H-SiC JFET Digital ICs Across 1000 C Temperature Range Without Change to Input Voltages

Operational testing of prototype 4H-SiC JFET ICs across an unrivaled ambient temperature span in excess of 1000 C, from -190 C to +812 C, has been demonstrated without any change/adjustment of input signal levels or power supply voltages. This unique ability is expected to simplify infusion of this IC technology into a broader range of beneficial applications

Lateral Growth Expansion of 4H/6H-SiC m-plane Pseudo Fiber Crystals by Hot Wall CVD Epitaxy

Lateral expansion of small mixed polytype 4H/6H-SiC slivers were realized by hot wall chemical vapor deposition (HWCVD). Small slivers cut from m-oriented ..11..00.. SiC boule slices containing regions of 4H and 6H SiC were exposed to HWCVD conditions using standard silane/propane chemistry for a period of up to eight hours. The slivers exhibited approximately 1500 microns (1.5 mm) of total lateral expansion. Initial analysis by synchrotron white beam x-ray topography (SWBXT) confirms, that the lateral growth was homoepitaxial, matching the polytype of the respective underlying region of the seed sliver

Electrical Characterization of 4H-SiC JFET Wafer: DC Parameter Variations for Extreme Temperature IC Design

This work reports DC electrical characterization of a 76 mm diameter 4H-SiC JFET test wafer fabricated as part of NASA's on-going efforts to realize medium-scale ICs with prolonged and stable circuit operation at temperatures as high as 500 degC. In particular, these measurements provide quantitative parameter ranges for use in JFET IC design and simulation. Larger than expected parameter variations were observed both as a function of position across the wafer as well as a function of ambient testing temperature from 23 degC to 500 degC

Electrical Performance of a High Temperature 32-I/O HTCC Alumina Package

A high temperature co-fired ceramic (HTCC) alumina material was previously electrically tested at temperatures up to 550 C, and demonstrated improved dielectric performance at high temperatures compared with the 96% alumina substrate that we used before, suggesting its potential use for high temperature packaging applications. This paper introduces a prototype 32-I/O (input/output) HTCC alumina package with platinum conductor for 500 C low-power silicon carbide (SiC) integrated circuits. The design and electrical performance of this package including parasitic capacitance and parallel conductance of neighboring I/Os from 100 Hz to 1 MHz in a temperature range from room temperature to 550 C are discussed in detail. The parasitic capacitance and parallel conductance of this package in the entire frequency and temperature ranges measured does not exceed 1.5 pF and 0.05 microsiemens, respectively. SiC integrated circuits using this package and compatible printed circuit board have been successfully tested at 500 C for over 3736 hours continuously, and at 700 C for over 140 hours. Some test examples of SiC integrated circuits with this packaging system are presented. This package is the key to prolonged T greater than or equal to 500 C operational testing of the new generation of SiC high temperature integrated circuits and other devices currently under development at NASA Glenn Research Center

CFD Growth of 3C-SiC on 4H/6H Mesas

This article describes growth and characterization of the highest quality reproducible 3C-SiC heteroepitaxial films ever reported. By properly nucleating 3C-SiC growth on top of perfectly on-axis (0001) 4H-SiC mesa surfaces completely free of atomic scale steps and extended defects, growth of 3C-SiC mesa heterofilms completely free of extended crystal defects can be achieved. In contrast, nucleation and growth of 3C-SiC mesa heterofilms on top of 4H-SiC mesas with atomic-scale steps always results in numerous observable dislocations threading through the 3C-SiC epilayer. High-resolution X-ray diffraction and transmission electron microscopy measurements indicate non-trivial in-plane lattice mismatch between the 3C and 4H layers. This mismatch is somewhat relieved in the step-free mesa case via misfit dislocations confined to the 3C/4H interfacial region without dislocations threading into the overlying 3C-SiC layer. These results indicate that the presence or absence of steps at the 3C/4H heteroepitaxial interface critically impacts the quality, defect structure, and relaxation mechanisms of single-crystal heteroepitaxial 3C-SiC films

Evidence of Processing Non-Idealities in 4H-SiC Integrated Circuits Fabricated With Two Levels of Metal Interconnect

The fabrication and prolonged 500 C electrical testing of 4H-SiC junction field effect transistor (JFET) integrated circuits (ICs) with two levels of metal interconnect is reported in another submission to this conference proceedings. While some circuits functioned more than 3000 hours at 500 C, the majority of packaged ICs from this wafer electrically failed after less than 200 hours of operation in the same test conditions. This work examines the root physical degradation and failure mechanisms believed responsible for observed large discrepancies in 500 C operating time. Evidence is presented for four distinct issues that significantly impacted 500 C IC operational yield and lifetime for this wafer

Evidence of Processing Non-Idealities in 4H-SiC Integrated Circuits Fabricated with Two Levels of Metal Interconnect

The fabrication and prolonged 500 C electrical testing of 4H-SiC junction field effect transistor (JFET) integrated circuits (ICs) with two levels of metal interconnect is reported in another submission to this conference proceedings. While some circuits functioned more than 1000 hours at 500 C, the majority of packaged ICs from this wafer electrically failed after less than 200 hours of operation in the same test conditions. This work examines the root physical degradation and failure mechanisms believed responsible for observed large discrepancies in 500 C operating time. Evidence is presented for four distinct issues that significantly impacted 500 C IC operational yield and lifetime for this wafer

Hydrogen Gas Sensors Fabricated on Atomically Flat 4H-SiC Webbed Cantilevers

This paper reports on initial results from the first device tested of a "second generation" Pt-SiC Schottky diode hydrogen gas sensor that: 1) resides on the top of atomically flat 4H-SiC webbed cantilevers, 2) has integrated heater resistor, and 3) is bonded and packaged. With proper selection of heater resistor and sensor diode biases, rapid detection of H2 down to concentrations of 20 ppm was achieved. A stable sensor current gain of 125 +/- 11 standard deviation was demonstrated during 250 hours of cyclic test exposures to 0.5% H2 and N2/air

Packaging Technologies for High Temperature Electronics and Sensors

This paper reviews ceramic substrates and thick-film metallization based packaging technologies in development for 500degC silicon carbide (SiC) electronics and sensors. Prototype high temperature ceramic chip-level packages and printed circuit boards (PCBs) based on ceramic substrates of aluminum oxide (Al2O3) and aluminum nitride (AlN) have been designed and fabricated. These ceramic substrate-based chiplevel packages with gold (Au) thick-film metallization have been electrically characterized at temperatures up to 550degC. A 96% alumina based edge connector for a PCB level subsystem interconnection has also been demonstrated recently. The 96% alumina packaging system composed of chip-level packages and PCBs has been tested with high temperature SiC devices at 500degC for over 10,000 hours. In addition to tests in a laboratory environment, a SiC JFET with a packaging system composed of a 96% alumina chip-level package and an alumina printed circuit board mounted on a data acquisition circuit board was launched as a part of the MISSE-7 suite to the International Space Station via a Shuttle mission. This packaged SiC transistor was successfully tested in orbit for eighteen months. A spark-plug type sensor package designed for high temperature SiC capacitive pressure sensors was developed. This sensor package combines the high temperature interconnection system with a commercial high temperature high pressure stainless steel seal gland (electrical feed-through). Test results of a packaged high temperature capacitive pressure sensor at 500degC are also discussed. In addition to the pressure sensor package, efforts for packaging high temperature SiC diode-based gas chemical sensors are in process