Compact modelling of the dynamic behaviour of MOSFETs

VII+168hlm.;24c

The influence of technology variation on ggNMOSTs and SCRs against CDM BSD stress

In this paper we present a systematic study on the effect of process and layout variation for grounded-gate NMOSTs and L VTSCRs in a 0.18μ,m technology under negative non-socketed Charged Device Model (CDM) stress. Failure Analysis of the stressed devices was done using Scanning Electron Microscopy (SEM). A comparison of the CDM test results with those of ggNMOSTs in various other technologies is also presented. It is shown that the CDM robustness of ggNMOSTs increases with technology scaling and that the performance ofL VTSCRs can be as good as that of ggNMOSTs under CDM stresses

Study on the influence of package parasitics and substrate resistance on the Charged Device Model(CDM) failure levels - possible protection methodology

Charged Device Model (CDM) type of Electrostatic Discharge (ESD) stress events are becoming the major reason for field returns in the Integrated Circuit (IC) industry especially with downscaling of device dimensions and increased usage of automated handlers. In the case of CDM stress, the IC is both the source of static charge and part of the discharge path. Hence CDM test results are greatly affected by the package properties and the distribution of the protection devices within the die. In this paper we present a systematic approach to understand the actual influence of these factors in the IC during a CDM event. The CDM test set-up is modeled using PSPICE circuit simulator and the discharge waveforms thus obtained are compared with the experimental observations. This model is then used to compare the actual discharge current flowing through the die and the protection structures for two different package materials. A general protection methodology for the ICs during CDM event, applicable to all IC design types, is suggested

Role of package parasitics and substrate resistance on the Charged Device Model (CDM) failure levels - An explantion and die protection strategy

With sownscaling of device dimensions and increased usage of automated handlers, Charged Device Model (CDM) type of Electrostatic Discharge (ESD) stress events are becoming the major readon for field returns in the Integrated Circuit (IC) industry. In the case of CDM stress, the IC is both the source of static charge and part od the discharge path. Hence CDM test results are greatly affected by the nature of the package, pin position and the location of the protection devices within the die. In this paper we present a systematic approach to understand the actual influence of these factors in the IC during a CDM event. The CDM test set-up is modeled using PSPICE circuit simulator and the discharge waveforms thus obtained are compared with the experimental observations. This model is then used to find the actual discharge current flowing through the die and the protection structures for different packages and pin positions. From this general protection strategy for CDM discharges, independent of the IC layout design is developed

Full chip model of CMOS Integrated Circuits under Charged Device Model stress

An ESD event which occurs when a charged IC touches a grounded surface is known as CDM type of ESD. The resulting static charge flow from CDM discharge causes large voltage overshoots across the IC causing gate-oxide damage. Measurements of exact internal voltage drops across the gate-oxide during CDM stress, is not possible because of the parasitic influence of the measurement set-up on the discharge path. This paper presents an efficient method of studying the voltage transients across the internal nodes of the IC during CDM stress, based circuit simulation. It presents a basic understanding of the charge flow during a CDM event, based on which an equivalent circuit model of the entire IC under CDM stress is developed. The correctness of the model is verified with the measurement data obtained for input protection structures in the 0.18μm CMOS technology node

Significance of Including Substrate Capacitance in the Full Chip Circuit Model of ICs under CDM Stress

In CDM type of ESD, the IC is both the source and part of discharge current path. To study the CDM performance of an ICI a full-chip circuit model that includes the various static charge sources and its discharge path through the circuit as it occurs in reality is needed. Static charge sources in a CDM event are rhe various package capacitors. The CDM circuit models presented before only include the capacitors formed by the IC circuit design on the package and not that of die attachment plate on which the die is placed. This paper emphasizes the need to include this capacitance and presents a simple method of including this capacitor and its discharge path through the circuit during CDM stress