Full chip model of CMOS Integrated Circuits under Charged Device Model stress

Abstract

An ESD event which occurs when a charged IC touches a grounded surface is known as CDM type of ESD. The resulting static charge flow from CDM discharge causes large voltage overshoots across the IC causing gate-oxide damage. Measurements of exact internal voltage drops across the gate-oxide during CDM stress, is not possible because of the parasitic influence of the measurement set-up on the discharge path. This paper presents an efficient method of studying the voltage transients across the internal nodes of the IC during CDM stress, based circuit simulation. It presents a basic understanding of the charge flow during a CDM event, based on which an equivalent circuit model of the entire IC under CDM stress is developed. The correctness of the model is verified with the measurement data obtained for input protection structures in the 0.18μm CMOS technology node