Carbon-related defects in Si:C/silicon heterostructures assessed by deep-level transient spectroscopy

This paper reports on a Deep-Level Transient Spectroscopy (DLTS) study of the electrically active defects in similar to 100 nm Si: C stressors, formed by chemical vapor deposition on p-type Czochralski silicon substrates. In addition, the impact of a post-deposition Rapid Thermal Annealing (RTA) at 850 degrees C on the DLT-spectra is investigated. It is shown that close to the surface at least two types of hole traps are present: one kind exhibiting slow hole capture, which may have a partial extended defect nature and a second type of hole trap behaving like a point defect. RTA increases the concentration of both hole traps and, in addition, introduces a point defect at EV + 0.35 eV in the depletion region of the silicon substrate at some distance from the Si: C epi layer. This level most likely corresponds with CiOi-related centers. Finally, a negative feature is found systematically for larger reverse bias pulses, which could point to a response of trap states at the Si: C/silicon hetero-interface

Study of electrically active defects in epitaxial layers on silicon

Electrically active defects in silicon-based epitaxial layers on silicon substrates have been studied by Deep-Level Transient Spectroscopy (DLTS). Several aspects have been investigated, like, the impact of the pre-epi cleaning conditions and the effect of a post-deposition anneal on the deep-level properties. It is shown that the pre-cleaning thermal budget has a strong influence on the defects at the substrate/epi layer interface. At the same time, a post-deposition Forming Gas Anneal can passivate to a large extent the active defect states. Finally, it is shown that application of a post-deposition anneal increases the out-diffusion of carbon from a Si:C stressor layer into the p-type CZ substrate

Low-frequency noise characterization of strained germanium pMOSFETs

Low-frequency noise in strained Ge epitaxial layers, which are grown on a reverse-graded relaxed SiGe buffer layer, has been evaluated for different front-end processing conditions. It has been shown that the 1/f noise in strong inversion is governed by trapping in the gate oxide (number fluctuations) and not affected by the presence of compressive strain in the channel. However, some impact has been found from the type of halo implantation used, whereby the lowest noise spectral density and the highest hole mobility are obtained by replacing the standard As halo by P implantation. At the same time, omitting the junction anneal results in poor device characteristics, which can be understood by considering the presence of a high density of nonannealed implantation damage in the channel and the gate stack near the source and the drain

Implantation and activation of Phosphorus in amorphous and crystalline Ge on Si

Germanium has interesting optical properties and high carrier mobilities, which can add functionality to Si CMOS. Doping of Ge can be achieved by introducing dopants during deposition (co-deposition) or by implantation after deposition. The disadvantage of implantation is the introduction of structural defects. To circumvent the introduction of structural defects during implantation of dopants, we have fabricated amorphous Ge (a-Ge) layers on Si. After implantation, the a-Ge layers were annealed to achieve solid phase epitaxy (SPE). As comparison, we have manufactured epitaxial Ge layers and introduced dopants by implantation and recrystallization. Further on we have fabricated a-Ge layers with co-doping of phosphorus, and crystallized this layer by SPE. XRD has been performed for structural analysis. SIMS is used to analyze the doping profile and diffusion of P. Hall effect is used to assess the resistivity, carrier concentration and mobility. Implantation and recrystallization of crystalline Ge shows better electrical results over implantation and activation of P dopants in a-Ge. Our results indicate limited influence of the Ge structure (amorphous or crystalline) on the dopant profile and diffusion after annealing. Furthermore the SPE process of amorphous layers is influenced when P is implanted. For a-Ge layers with P co-doping, SPE gives excellent electrical activation. Finally, the annealing conditions have significant influence on the amorphous layers when implanted.status: publishe

Implantation and activation of phosphorus in amorphous and crystalline germanium layers

We have investigated phosphorus implantation and activation in amorphous and crystalline Ge layers, deposited on Si substrates. The structure of the Ge layer has only limited influence on the dopant profile and diffusion after annealing. Surprisingly, crystalline Ge layers show better electrical results after implantation and dopant activation. For the amorphous layer, the solid phase epitaxy process is influenced in the neighborhood of P, leading to point defects, which inhibit electrical activation. This result implies that when a crystalline Ge layer is amorphized during implantation of high doses, the dopant activation can be significantly reduced. Reduced temperature ramping improves activation of P in amorphous Ge layers.status: publishe

Defect-related excess low-frequency noise in Ge-on-Si pMOSFETs

The low-frequency noise in strained and relaxed Ge pMOSFETs is characterized to investigate more closely the anomalously large current spectral density at low drain currents. As shown, the dominant Lorentzian spectrum found in weak inversion points to fluctuations by generation-recombination (GR) events at substrate defects. This is confirmed by the fact that strained Ge transistors, having a significantly lower threading dislocation density, also exhibit lower excess GR noise. The usual number-fluctuation 1/f noise becomes more pronounced above threshold and also for shorter gate lengths