Fully Integrated CMOS Phase-Locked Loop With 30MHz to 2GHz Locking Range and +-35ps Jitter

A fully integrated phase-locked loop (PLL) fabricated in a 0.24 micrometer, 2.5v digital CMOS technology is described. The PLL is intended for use in multi-gigabit-per-second clock recovery circuits in fiber-optic communication chip. This PLL first time achieved a very large locking range measured to be from 30MHz up to 2GHz in 0.24 micrometer CMOS technology. Also it has very low peak-to-peak jitter less than +-35ps at 1.25GHz output frequency

A Fully Integrated CMOS Phase-Locked Loop With 30MHz to 2GHz Locking Range and ±35 ps Jitter

A fully integrated phase-locked loop (PLL) fabricated in a 0.24μm, 2.5v digital CMOS technology is described. The PLL is intended for use in multi-gigabit-per-second clock recovery circuits in fiber-optic communication chips. This PLL first time achieved a very large locking range measured to be from 30MHz up to 2GHz in 0.24μm CMOS technologies. Also it has very low peak-to-peak jitter less than ±35ps at 1.25GHz output frequency

An Extended Frequency Range CMOS Voltage-Controlled Oscillator

This paper presents an extended frequency range CMOS monolithic voltage-controlled oscillator (VCO) design. A negative feedback control algorithm is used to automatically adjust the VCO range according to the control voltage. Based on this analog feedback control algorithm, the VCO achieves a wide range without any pre-register settings. Low phase noise is achieved by using both coarse control and fine control in VCO. A 600 MHz to 3.3 GHz monolithic CMOS PLL based on this wide range and low phase noise VCO has been fabricated in TSMC 0.18 μm, 1.8V CMOS technology and is used in many different applications such as FC, GE, and SONET etc