Comprehensive identification of sensitive and stable ISFET sensing layer high-k gate based on ISFET/electrolyte models

The ISFET sensing membrane is in direct contact with the electrolyte solution, determining the starting sensitivity of these devices. A SiO2 gate dielectric shows a low response sensitivity and poor stability. This paper proposes a comprehensive identification of different high-k materials which can be used for this purpose, rather than SiO2. The Gouy-Chapman and Gouy-Chapman-Stern models were combined with the Site-binding model, based on surface potential sensitivity, to achieve the work objectives. Five materials, namely Al2O3, Ta2O5, Hfo2, Zro2 and SN2O3, which are commonly considered for micro-electronic applications, were compared. This study has identified that Ta2O5 have a high surface potential response at around 59mV/pH, and also exhibits high stability in different electrolyte concentrations. The models used have been validated with real experimental data, which achieved excellent agreement. The insights gained from this study may be of assistance to determine the suitability of different materials before progressing to expensive real ISFET fabrication

Geometric and process design of ultra-thin junctionless double gate vertical MOSFETs

The junctionless MOSFET architectures appear to be attractive in realizing the Moore’s law prediction. In this paper, a comprehensive 2-D simulation on junctionless vertical double-gate MOSFET (JLDGVM) under geometric and process consideration was introduced in order to obtain excellent electrical characteristics. Geometrical designs such as channel length (Lch) and pillar thickness (Tp) were considered and the impact on the electrical performance was analyzed. The influence of doping concentration and metal gate work function (WF) were further investigated for achieving better performance. The results show that the shorter Lch can boost the drain current (ID) of n-JLDGVM and p-JLDGVM by approximately 68% and 70% respectively. The ID of the n-JLVDGM and p-JLVDGM could possibly boost up to 42% and 78% respectively as the Tp is scaled down from 11nm to 8nm. The channel doping (Nch) is also a critical parameter, affecting the electrical performance of both n-JLDGVM and p-JLDGVM in which 15% and 39% improvements are observed in their respective ID as the concentration level is increased from 1E18 to 9E18 atom/cm3. In addition, the adjustment of threshold voltage can be realized by varying the metal WF

Comparison of Electrical Characteristics between Bulk MOSFET and Silicon-on-Insulator (SOI) MOSFET

Conventional MOSFET has already passed lower than 45nm transistorfabrication. As silicon is now hitting the atomic resolution and reaching its physical and electrical limitation, producing a proper working transistor tends to be more difficult and complicated. The major challenge is to fabricate a transistor with anominal threshold voltage (VTH), lower gate leakage current (IOFF) and lower drain induced barrier lowering (DIBL). To overcome these problems, Siliconon-insulator (SOI) MOSFET has been proposed, and it is believed to be capable of suppressing short channel effects (SCEs) by burying oxide layer in the silicon substrate. ATHENA and ATLAS module of SILVACO software were used in simulating the virtual fabrication and electrical performance of the transistors. An investigation on the characteristics and performance of the devices has been conducted in order to compare their electrical characteristics. The MOSFETstructure was constructed byutilizingSILVACO Athenamodule,and the electrical characteristicswere simulated using SILVACO Atlas module. The results of boththe conventional bulk MOSFET and the SOI MOSFETwere analyzed. It was observed that SOI MOSFET was superior compared to the conventional MOSFET interms of their overallelectrical characteristic

Implementation of Taguchi Modeling for Higher Drive Current (ION) in Vertical DG-MOSFET Device

Vertical Double-Gate (DG) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is capable to minimize various short channel effect (SCEs) problems. Vertical DG-MOSFET is constructed by having two gates that are able to control the channel from both sidesand has better electrostatic control over the channel. Meanwhile, the drive current (ION) should be maintained above 0.2mA in order to decide the driving capability of the device. The drive current (ION) must be set at high value so that the transistor acquires superb driving characteristicsthat are capable to switch the device into on-state condition. This paper describes the design of a vertical DGMOSFET, while keeping the drive current (ION) as maximum as possible, by utilizing both SILVACO TCAD software and statistical methods. Based on the ANOVA method, factor E (Halo Implant Energy –45%), factor F (Halo Implant Tilt –22%) and factor L (Compensation Implant Energy – 15.78%) were recognized as the most significant factors. The maximum value of drive current (ION) was observed to be at 0.3291 mA/µm with signal-to-noise ratio of -10.00dB

Optimization of Electrical Properties in TiO2/WSix-based Vertical DG-MOSFET using Taguchi-based GRA with ANN

This study describes a proposed method to determine the most optimal level of process parameters, considering multiple electrical properties of titanium dioxide/tungsten silicide (TiO2/WSix)-based vertical double-gate MOSFET. The proposed method utilizes a combination of the L9 orthogonal array (OA) of Taguchi-based grey relational analysis (GRA) and the artificial neural network (ANN). The VTH implant energy, halo implant dose, source/drain (S/D) implant dose and S/D implant tilt angle are the selected processs parameters to be optimized for the optimal value of on-current (ION), off-current (IOFF) and subthreshold slope (SS). The design of experiment (DoE) is based on the L9 OA of Taguchi method and the experimental value for multiple electrical properties are converted into a grey relational grade (GRG). The well-trained ANN based on the Levenberg-Marquardt algorithm is developed to predict the best optimization results. The most optimal level of four process parameters towards ION, IOFF and SS are selected based on the highest GRG predicted by welltrained ANN. The most optimal value for ION, IOFF and SS after the optimization are observed to be 1612.1 µA/µm, 8.801E-10 A/µm and 67.74 mV/dec respectively with 0.7417 of predicted GRG

Impact of Salicide and Source/Drain Implants on Leakage Current and Sheet Resistance in 45nm NMOS Device

In this paper, we investigate the impact of Source/Drain (S/D) implant and salicide on poly sheet resistance (RS) and leakage current (I Leak ) in 45nm NMOS device performance. The experimental studies were conducted under varying four process parameters, namely Halo implant, Source/Drain Implant, Oxide Growth Temperature and Silicide Anneal Temperature. Taguchi Method was used to determine the settings of process parameters. The level of importance of the process parameters on the RS and I Leak were determined by using analysis of variance (ANOVA). The fabrication of the devices was performed by using fabrication simulator of ATHENA. The electrical characterization of the device was implemented by using electrical characterization simulator of ATLAS. These two simulators were combined with Taguchi method to aid in design and optimizing the process parameters. The optimum process parameter combination was obtained by using the analysis of signal-tonoise (S/N) ratio. In this research, the most effective process parameters with respect to poly sheet resistance and leakage current are silicide anneal temperature (88%) and S/D implant (62%) respectively. Whereas the second ranking factor affecting the poly sheet resistance and leakage current are S/D implant (12%) and silicide anneal temperature (20%) respectively. As conclusions, S/D implant and silicide annealtemperature have the strongest effect on the response characteristics. The results show that the R S and I Leak after optimizations approaches are 42.28□□ and 0.1186mA/□m respectivel

Performance analysis of ultrathin junctionless double gate vertical MOSFETs

The main challenge in MOSFET minituarization is to form an ultra-shallow source/drain (S/D) junction with high doping concentration gradient, which requires an intricate S/D and channel engineering. Junctionless MOSFET configuration is an alternative solution for this issue as the junction and doping gradients is totally eliminated. A process simulation has been developed to investigate the impact of junctionless configuration on the double-gate vertical MOSFET. The result proves that the performance of junctionless double-gate vertical MOSFETs (JLDGVM) are superior to the conventional junctioned double-gate vertical MOSFETs (JDGVM). The results reveal that the drain current (ID) of the n-JLVDGM and p-JLVDGM could be tremendously enhanced by 57% and 60% respectively as the junctionless configuration was applied to the double-gate vertical MOSFET. In addition, junctionless devices also exhibit larger ION/IOFF ratio and smaller subthreshold slope compared to the junction devices, implying that the junctionless devices have better power consumption and faster switching capability

Response Surface Approach to Optical Channel Dropping Filter Design Parameters Optimization

The objective of this paper is to optimise the design parameters for the optical channel dropping filter, which is based on the microring resonator topology. The most important parameters to determine the performance of the microring channel optical filter are the waveguide width, gap, core thickness and ring radius. The determination of parameters by classical experimental design methods requires a large amount of experimental data, which has been found to be costly and time-consuming. To overcome this drawback, a design of experiment (DOE) methods of the Response Surface Methodology (RSM) was employed. This paper employed the RSM design analysis in evaluating the performance of the microring resonator with different design parameters settings. Upon completion, the RSM shows that the optimum condition can be achieved when the ring radius is 5.50μm, a gap of 200nm, waveguide width of 418 nm and core thickness of 220 nm. In conclusion, for optimized performance of the channel dropping filter, design conditions within the range demonstrated in this study are suggested