Journal of Telecommunication, Electronic and Computer Engineering (JTEC)
Abstract
In this paper, we investigate the impact of Source/Drain (S/D) implant and salicide on poly sheet resistance (RS) and leakage current (I Leak ) in 45nm NMOS device performance. The experimental studies were conducted under varying four process parameters, namely Halo implant, Source/Drain Implant, Oxide Growth Temperature and Silicide Anneal Temperature. Taguchi Method was used to determine the settings of process parameters. The level of importance of the process parameters on the RS and I Leak were determined by using analysis of variance (ANOVA). The fabrication of the devices was performed by using fabrication simulator of ATHENA. The electrical characterization of the device was implemented by using electrical characterization simulator of ATLAS. These two simulators were combined with Taguchi method to aid in design and optimizing the process parameters. The optimum process parameter combination was obtained by using the analysis of signal-tonoise (S/N) ratio. In this research, the most effective process parameters with respect to poly sheet resistance and leakage current are silicide anneal temperature (88%) and S/D implant (62%) respectively. Whereas the second ranking factor affecting the poly sheet resistance and leakage current are S/D implant (12%) and silicide anneal temperature (20%) respectively. As conclusions, S/D implant and silicide annealtemperature have the strongest effect on the response characteristics. The results show that the R S and I Leak after optimizations approaches are 42.28□□ and 0.1186mA/□m respectivel
