Interface Synthesis for Embedded Applications in a Codesign Environment

In embedded systems, programmable peripherals are often coupled with the main programmable processor to achieve desired functionality. Interfacing such peripherals with the processor qualifies as an important task of hardware software codesign. In this paper, three important aspects of such interfacing, namely the allocation of addresses to the devices, allocation of device drivers, and approaches to handle events and transitions have been discussed. The proposed approaches have been incorporated in a codesign system MICKEY. The paper includes a number of examples, taken from the results synthesized by MICKEY, to illustrate the ideas

Neurologic phenotype of Schimke immuno-osseous dysplasia and neurodevelopmental expression of SMARCAL1

Schimke immuno-osseous dysplasia (OMIM 242900) is an uncommon autosomal-recessive multisystem disease caused by mutations in SMARCAL1 (swi/snf-related, matrix-associated, actin-dependent regulator of chromatin, subfamily a-like 1), a gene encoding a putative chromatin remodeling protein. Neurologic manifestations identified to date relate to enhanced atherosclerosis and cerebrovascular disease. Based on a clinical survey, we determined that half of Schimke immuno-osseous dysplasia patients have a small head circumference, and 15% have social, language, motor, or cognitive abnormalities. Postmortem examination of 2 Schimke immuno-osseous dysplasia patients showed low brain weights and subtle brain histologic abnormalities suggestive of perturbed neuron-glial migration such as heterotopia, irregular cortical thickness, incomplete gyral formation, and poor definition of cortical layers. We found that SMARCAL1 is highly expressed in the developing and adult mouse and human brain, including neural precursors and neuronal lineage cells. These observations suggest that SMARCAL1 deficiency may influence brain development and function in addition to its previously recognized effect on cerebral circulation

A Low Cost Concept for Data Acquisition Systems Applied to Decentralized Renewable Energy Plants

The present paper describes experiences of the use of monitoring and data acquisition systems (DAS) and proposes a new concept of a low cost DAS applied to decentralized renewable energy (RE) plants with an USB interface. The use of such systems contributes to disseminate these plants, recognizing in real time local energy resources, monitoring energy conversion efficiency and sending information concerning failures. These aspects are important, mainly for developing countries, where decentralized power plants based on renewable sources are in some cases the best option for supplying electricity to rural areas. Nevertheless, the cost of commercial DAS is still a barrier for a greater dissemination of such systems in developing countries. The proposed USB based DAS presents a new dual clock operation philosophy, in which the acquisition system contains two clock sources for parallel information processing from different communication protocols. To ensure the low cost of the DAS and to promote the dissemination of this technology in developing countries, the proposed data acquisition firmware and the software for USB microcontrollers programming is a free and open source software, executable in the Linux and Windows® operating systems

Degradation of MONOCULM 1 by APC/CTAD1 regulates rice tillering

A rice tiller is a specialized grain-bearing branch that contributes greatly to grain yield. The MONOCULM 1 (MOC1) gene is the first identified key regulator controlling rice tiller number; however, the underlying mechanism remains to be elucidated. Here we report a novel rice gene, Tillering and Dwarf 1 (TAD1), which encodes a co-activator of the anaphase-promoting complex (APC/C), a multi-subunit E3 ligase. Although the elucidation of co-activators and individual subunits of plant APC/C involved in regulating plant development have emerged recently, the understanding of whether and how this large cell-cycle machinery controls plant development is still very limited. Our study demonstrates that TAD1 interacts with MOC1, forms a complex with OsAPC10 and functions as a co-activator of APC/C to target MOC1 for degradation in a cell-cycle-dependent manner. Our findings uncovered a new mechanism underlying shoot branching and shed light on the understanding of how the cell-cycle machinery regulates plant architecture

Software Synthesis and Code Generation for Signal Processing Systems

The role of software is becoming increasingly important in the implementation of DSP applications. As this trend intensifies, and the complexity of applications escalates, we are seeing an increased need for automated tools to aid in the development of DSP software. This paper reviews the state of the art in programming language and compiler technology for DSP software implementation. In particular, we review techniques for high level, block-diagram-based modeling of DSP applications; the translation of block diagram specifications into efficient C programs using global, target-independent optimization techniques; and the compilation of C programs into streamlined machine code for programmable DSP processors, using architecture-specific and retargetable back-end optimizations. We also point out important directions for further investigation

Versatile System-level Memory-aware Platform Description Approach for embedded MPSoCs

In this paper, we present a novel system modeling language which targets primarily the development of source-level multiprocessor memory aware optimizations. In contrast to previous system modeling approaches this approach tries to model the whole system and especially the memory hierarchy in a structural and semantically accessible way. Previous approaches primarily support generation of simulators or retargetable code selectors and thus concentrate on pure behavioral models or describe only the processor instruction set in a semantically accessible way, A simple, database-like, interface is offered to the optimization developer, which in conjunction with the MACCv2 framework enables rapid development of source-level architecture independent optimizations.45491

Bus-aware multicore WCET analysis through TDMA offset bounds

10.1109/ECRTS.2011.9Proceedings - Euromicro Conference on Real-Time Systems3-1