Coarse-grained reconfigurable array architectures

Coarse-Grained Reconfigurable Array (CGRA) architectures accelerate the same inner loops that benefit from the high ILP support in VLIW architectures. By executing non-loop code on other cores, however, CGRAs can focus on such loops to execute them more efficiently. This chapter discusses the basic principles of CGRAs, and the wide range of design options available to a CGRA designer, covering a large number of existing CGRA designs. The impact of different options on flexibility, performance, and power-efficiency is discussed, as well as the need for compiler support. The ADRES CGRA design template is studied in more detail as a use case to illustrate the need for design space exploration, for compiler support and for the manual fine-tuning of source code

Development of weather-based predictive models for Fusarium head blight and Deoxynivalenol accumulation for spring malting barley

The associations between Fusarium head blight (FHB), caused by Gibberella zeae, and deoxynivalenol (DON) accumulation in spring malting barley (Hordeum vulgare) and hourly weather conditions predictive of DON accumulation were examined using data from six growing seasons in the U.S. Northern Great Plains. Three commonly grown cultivars were planted throughout the region, and FHB disease and DON concentration were recorded. Nine predictor variables were calculated using hourly temperature and relative humidity during the 10 days preceding full head spike emergence. Simple logistic regression models were developed using these predictor variables based on a binary threshold for DON of 0.5 mg/kg. Four of the nine models had sensitivity greater than 80%, and specificity of these models ranged from 67 to 84% (n = 150). The most useful predictor was the joint effect of average hourly temperature and a weighted duration of uninterrupted hours (h) with relative humidity greater than or equal to 90%. The results of this study confirm that FHB incidence is significantly associated with DON accumulation in the grain and that weather conditions prior to full head emergence could be used to accurately predict the risk of economically significant DON accumulation for spring malting barley

Computation Models for Reconfigurable Machines

: Currently, reconfigurable computing solutions are developed by writing High level Description Language (HDL) code and compiling it onto hardware. Though this approach is suitable for static reconfigurable devices, tools using this approach do not analyze the runtime behavior of the application. Hence designing tools which exploit dynamic reconfigurability is not an easy task. This paper presents a new approach to developing dynamically reconfigurable computing solutions. Computing models are developed which bridge the semantic gap between the algorithm and the actual hardware. A General Reconfigurable Computing Model (GRECOM) is used to capture the ability to change both the interconnections and the logic at runtime based on intermediate results. Two specific instances of GRECOM, the Reconfigurable Mesh and the FPGA Model are derived and applications are demonstrated using these models. 1 This work was supported by DARPA under contract DABT63-96-C-0049 monitored by Fort Hauchuca. ..

A stochastic bitwidth estimation technique for compact and low-power custom processors

There is an increasing trend toward compiling from C to custom hardware for designing embedded systems in which the area and power consumption of application-specific functional units, registers, and memory blocks are heavily dependent on the bit-widths of integer operands used in computations. The actual bit-width required to store the values assigned to an integer variable during the execution of a program will not, in general, match the built-in C data types. Thus, precious area is wasted if the built-in data type sizes are used to declare the size of integer operands. In this paper, we introduce stochastic bit-width estimation that follows a simulation-based probabilistic approach to estimate the bit-widths of integer variables using extreme value theory. The estimation technique is also empirically compared to two compile-time integer bit-width analysis techniques. Our experimental results show that the stochastic bit-width estimation technique dramatically reduces integer bit-widths and, therefore, enables more compact and power-efficient custom hardware designs than the compile-time integer bit-width analysis techniques. Up to 37% reduction in custom hardware area and 30% reduction in logic power consumption using stochastic bit-width estimation can be attained over ten integer applications implemented on an FPGA chip