Inertial and Degradation Delay Model for CMOS Logic Gates

The authors present the Inertial and Degradation Delay Model (IDDM) for CMOS digital simulation. The model combines the Degradation Delay Model presented in previous papers with a new algorithm to handle the inertial effect, and is able to take account of the propagation and filtering of arbitrarily narrow pulses (glitches, etc.). The model clearly overcomes the limitations of conventional approaches

NanoFS: a hardware-oriented file system

NanoFS is a novel file system for embedded systems and storage-class memories (like flash) and is specially designed to be directly implemented in hardware. NanoFS is based on an original internal layout intended to achieve an optimal hardware implementation of the file system’s file lookup and data fetch operations. File system spe-cification on a sample reader module completely implemented in a pro-grammable device is introduced

Sistemas de control de grupos de prácticas. Aplicación al ámbito docente del Departamento de Tecnología Electrónica de laUniversidad de Sevilla

En este trabajo, se presenta un sistema automático, basado en web, orientado a facilitar la organización de prácticas de laboratorio en asignaturas con elevado número de alumnos. Se caracteriza por permitir tanto su utilización como su administración mediante browser, cumplir con los necesarios requisitos de seguridad, y soportar acceso a los datos de forma concurrente. Además, la implantación se ha realizado mediante software de libre distribución lo que demuestra, una vez más, la viabilidad e idoneidad de este tipo de plataformas

Minimalistic SDHC-SPI hardware reader module for boot loader applications

This paper introduces a low-footprint full hardware boot loading solution for FPGA-based Programmable Systems on Chip. The proposed module allows loading the system code and data from a standard SD card without having to re-program the whole embedded system. The hardware boot loader is processor independent and removes the need of a software boot loader and the related memory resources. The hardware overhead introduced is manageable, even in low-range FPGA chips, and negligible in mid- and high-range devices. The implementation of the SD card reader module is explained in detail and an example of a multi-boot loader is offered as well. The multi-boot loader is implemented and tested with the Xilinx's Picoblaze microcontroller

Aprendizaje interdisciplinar de la electrónica y las comunicaciones

En este proyecto de innovación docente se pretende profundizar en el conocimiento de la base teórica, la construcción de los modelos matemáticos físicos que son la base de los diseños electrónicos, mediante el montaje, presentación, simulación y experimentación. El procedimiento se basa en la realización de medidas experimentales básicas a principio de curso y en las aplicaciones interdisciplinares a final de curso, así como disponer de todo el material vía Internet para motivar el aprendizaje del alumno.The aim of this teaching innovation project is to look for deeply into knowledge about the theoretical base and construction of mathematical models that are the basis of electrical design, making use of setups, lectures, simulations and experimentations. The procedure is based upon the execution of essential experimental measurements at the beginning of the school year and on interdisciplinary applications at the end of it, all complemented with related Internet resources targeted to improve student motivation

Fast-Convergence Microsecond-Accurate Clock Discipline Algorithm for Hardware Implementation

Discrete microprocessor-based equipment is a typical synchronization system on the market which implements the most critical features of the synchronization protocols in hardware and the synchronization algorithms in software. In this paper, a new clock discipline algorithm for hardware implementation is presented, allowing for full hardware implementation of synchronization systems. Measurements on field-programmable gate array prototypes show a fast convergence time (below 10 s) and a high accuracy (1 μs) for typical configuration parameters.Ministerio de Educación y Cultura HIPER TEC2007-61802/MI

Characterization of Normal Propagation Delay for Delay Degradation Model (DDM)

12th International Workshop, PATMOS: : International Workshop on Power and Timing Modeling, Optimization and Simulation, Seville, Spain, September 11–13, 2002 ISBN: 978-3-540-44143-4In previous papers we have presented a very accurate model that handles the generation and propagation of glitches, which makes an important headway in logic timing simulation. This model is called Delay Degradation Model (DDM). Characterizing DDM completely also implies the characterization of the normal propagation delay. In this paper, we propose a simple heuristic model that includes its dependence on the output load and the input transition time. We have tested this model and found a mean deviation lower than 4%. Also, we present a characterization process for this model that is fully integrated into AUTODDM without affecting the total simulation time needed to characterize a standard cell.Ministerio de Ciencia y Tecnología MODEL TIC 2000-1350Ministerio de Ciencia y Tecnología VERDI TIC 2002-228

Automated performance evaluation of skew-tolerant clocking schemes

In this paper the authors evaluate the timing and power performance of three skew-tolerant clocking schemes. These schemes are the well known master–slave clocking scheme (MS) and two schemes developed by the authors: Parallel alternating latches clocking scheme (PALACS) and four-phase parallel alternating latches clocking scheme (four-phase PALACS). In order to evaluate the timing performance, the authors introduce algorithms to obtain the clock waveforms required by a synchronous sequential circuit. Separated algorithms were developed for every clocking scheme. From these waveforms it is possible to get parameters such as the non-overlapping time and the clock period. They have been implemented in a tool and have been used to compare the timing performance of the clocking schemes applied to a simple circuit. To analyse the power consumption the authors have electrically simulated a simple circuit for several operation frequencies. The most remarkable conclusion is that it is possible to save about 50% of the power consumption of the clock distribution network by using PALACS.Ministerio de Ciencia y Tecnología TEC 2004-00840/MI

Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level

This contribution presents a method to obtain current estimations at the logic level. This method uses a simple current model and a current curve generation algorithm that is implemented as an attached module to a logic simulator under development called HALOTIS. The implementation is aimed at efficiency and overall estimations, making it suitable to switching noise evaluation and current peaks localisation. Simulation results and comparison to HSPICE confirm the usefulness and efficiency of the approach.Ministerio de Ciencia y Tecnología MODEL project TIC 2000-1350Ministerio de Ciencia y Tecnología VERDI project TIC 2002-228

HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model

This communication presents HALOTIS, a novel high accuracy logic timing simulation tool, that incorporates a new simulation algorithm based on different concepts for transitions and events. This new simulation algorithm is intended for including the inertial and degradation delay models. Simulation results are very similar to those obtained by electrical simulators, and show a higher accuracy compared to conventional delay models implemented in current logic simulators.Ministerio de Ciencia y Tecnología TIC 2000-135