This communication presents HALOTIS, a novel high
accuracy logic timing simulation tool, that incorporates a
new simulation algorithm based on different concepts for
transitions and events. This new simulation algorithm is
intended for including the inertial and degradation delay
models. Simulation results are very similar to those
obtained by electrical simulators, and show a higher
accuracy compared to conventional delay models
implemented in current logic simulators.Ministerio de Ciencia y Tecnología TIC 2000-135

Acosta Jiménez, Antonio José

Bellido Díaz, Manuel Jesús

Juan Chico, Jorge

Ruiz de Clavijo Vázquez, Paulino

Valencia Barrero, Manuel

idUS. Depósito de Investigación Universidad de Sevilla

HALOTIS: High Accuracy LOgic TIming Simulator with inertial and degradationdelay modelRuiz de Clavijo Vazquez, P1. ; Juan-Chico, J1. ; Bellido, M.J1. ; Acosta, A2. and Valencia, M.1Instituto de Microelectronica de Sevilla. CNMEdificio CICA, Avda/ Reina Mercedes s/n 41012-Sevilla. Spain{paulino,jjchico,bellido,acojim,manolov}@imse.cnm.es1 also with Dpto. de Tecnologia Electronica. Universidad de Sevilla2 also with Dpto. de Electronica y Electromagnetismo. Universidad de SevillaTlf. +34-955056666 Fax. +34-955056686AbstractThis communication presents HALOTIS, a novel highaccuracy logic timing simulation tool, that incorporates anew simulation algorithm based on different concepts fortransitions and events. This new simulation algorithm isintended for including the inertial and degradation delaymodels. Simulation results are very similar to thoseobtained by electrical simulators, and show a higheraccuracy compared to conventional delay modelsimplemented in current logic simulators.1. IntroductionAs digital circuits become larger and faster, better anal-ysis tools are required. It means that logic simulators mustbe able to handle bigger circuitry in a more accurate way.Simulating large circuits is aided by the evolution of com-puter systems capabilities, and accuracy is improved byproviding more realistic delay models.Currently, there exist accurate delay models for CMOSdigital circuits which take account of most modern issues[1, 2, 3, 4]: low voltage operation, sub-micron and deepsub-micron devices, transition waveforms, etc. Besidesthese effects, there are also dynamic situations whichshould be handled by the delay model. The most importantdynamic effects are the so-called input collisions [5]: thegate’s behavior when two or more input transitions happenclose in time may be quite different from the response to anisolate input transition. Of all these input collisions, thereis a special interest in the glitch collisions, which are thosethat might cause an output glitch. Being able to handlethese glitch collisions is important since they are more andmore likely to happen in current fast circuits, and it willhelp us to determine race conditions and truly power con-This work has been sponsored in part by the MCYT underProject TIC 2000-1350sumption due to glitches [6,7]. This is also strongly relatedto the modeling of the inertial effect [8], which determineswhen a glitch is filtered, and to the triggering of metastablebehavior in latches [9, 10, 11, 12]. Other authors have dealwith the problem of glitches, either partially or not veryaccurately [5, 6, 7, 13].In [14, 15, 16, 17] a new model denominated Inertialand Degradation Delay Model (IDDM) has been intro-duced. This model combines the degradation effect ofglitches with a new algorithm to handle the inertial effect.When trying to incorporate this model in the current logic-timing simulators, as VHDL standard simulator or VER-ILOG, there are many problems difficult to solve since thenew proposed approach dealing with degradation and iner-tial effects significantly affects the simulation algorithmitself. Therefore it is necessary to build a new logic-timingsimulation tools based on the new algorithm to include theIDDM.In this paper we present a new logic-timing simulatorcalled HALOTIS including the IDDM. The work is orga-nized as follows. In the next section we resume the IDDM.In the third section we describe the new simulation algo-rithm implemented in HALOTIS. As it will be shown, themost interesting aspects of HALOTIS is the novel dealingof stimuli in signals and the simulation algorithm. Resultsof simulation are presented in fourth section, showing agood agreement with electrical simulation, and CPU timevery similar to those from other logic simulators. Lately,we present the most important conclusions of the work.2. The IDDM modelTypical models for logic simulation only consider theinertial effect to deal with very narrow pulses. These mod-els show a discontinuous behavior for very similar inputconditions. This discontinuity is due to the fact thatdepending on its width, an input pulse may be in a normalpropagation or a filtering (non-propagation) region. How-ever, the change in the behavior of a true gate is not abrupt,rather continuous and gradual. In fact, two limit casesappear in real behavior: one for wide pulses that are propa-gated normally and another for very narrow pulses that areeliminated, but there is a pulse-width range between themin which pulses are neither eliminated nor propagated nor-mally. Inside this range, the output pulse width is smallerthan the corresponding input pulse width. In such a case,the pulse is considered to be degraded.We showed in [15,16,17] that the delay decreases expo-nentially as pulses are shortened. Full degradation effectinsights were studied for the case of CMOS gates and adelay model that takes into account the exponential behav-ior of the degradation effect was also presented. The mainresults of this model can be summarized as follows: onlytwo parameters for each type of transition, and , areneeded to model the degradation effect, resulting in the fol-lowing formula:(eq. 1)where is the normal propagation delay, that can becalculated using a conventional delay model [1, 2], is thetime elapsed since the last output transition in the gate'soutput took place, which measures the internal state of thegate, and and are the degradation parameters whichdepend on the output load ( ), the supply voltage ( ),the input transition time ( ) and the position of the inputthat is changing state ( ). It has been obtained in [15] thatthis dependence can be expressed as:(eq. 2)(eq. 3)where “x” stands for “r” or “f” depending on the sense ofthe output transition (rise or fall respectively).Glitch degradation should be combined with inertialeffect because, after sucesive degradations, a runt pulse willbe eliminated. In [14] we have demostrated that the conven-tional model for inertial effect, defined as an inertial delay,may produce wrong results in a logic simulation. This canbe observed in Figure 1 and, as consequence, the accuracyof the simulation decreases. In this work we propose a newtreatment for the inertial effect, that together with the DDMmodel results in the IDDM model: Inertial and DegradationDelay Model.The basic difference between current models for theinertial effect and the proposed model, lies in the choice ofthe exact place where pulses are filtered. In classical mod-els, one pulse is rejected at the output of a gate if whenpropagating through the gate, it does not reach the middlepoint of the logic swing, meaning that the pulse does notexist for any gate’s input connected to this output signal.However, in our proposal, any output pulse is taken intoaccount, even if it does not reach the middle point of thelogic swing. At the inputs of the gates connected to this out-put, it is decided if this pulse is able to produce a transitionin those gates or not. In this way is possible that a smallpulse, can be propagated through one or more gates, whilecannot be propagated through other different gates con-nected to the same signal.With this idea, in [14] it is provided the model with anew parameter VT that is the voltage threshold associated tothe gate input. A pulse in input is only propagated if itcrosses the VT value.It is important to notice that, in order to implement thismodel in a logic-timing simulator, it is necessary to handlesignals with both timing and voltage parameters. For thisreason it is not possible to include this model in currentlogic simulation tools. We have developed a simulatoradapted to IDDM which contains a new simulation algo-rithm as shows next section.3. HALOTIS SimulatorAs it was previously mentioned, we have developed anew logic timing simulator named HALOTIS. Figure 2shows the class diagram of HALOTIS, where the relationsbetween the implemented data structures can be seen. Themain characteristics of this simulator are the new way todeal with stimuli and a novel simulation algorithm.τ T 0t p t p0 1 eT T 0–τ---------------  ––    =t p0Tτ T 0CL V DDτiniτxV DD Axi BxiCL+=T 0x12--CxiV DD-----------–   τin=inverterout1out2out1cout2c0 1 2 3 4 5012345VT2VT1 Ving1g2inV outg2g1g0chaininverterchainout00 1 2 30123450 1 2 3012345inout0out1out1cout2out2c0 1 2 3VT2VT1inout0out1out1cout2out2c(a)Figure 1. Inertial delay wrong results. a) Simulatedcircuit and transfer characteristics of inverters. b)HSPICE simulation results. c) Logic simulationresults using the inertial delay model.(b) (c)3.1 Dealing with stimulis.To improve simulation accuracy, we distinguishbetween “transition” and “event”. A transition is a signalchanging from “0” to “1” or “1” to “0”. They are approxi-mated by a linear curve and determined by the rise or falltime (τx) and the instant when the transition begins (t0). Asgate inputs may have individual input thresholds (Vt), a sin-gle transition may trigger a gate activation at different volt-ages, which means different times for a signal that driversvarious gate’s inputs (Figure 3). Each time a transitioncrosses an input threshold, an event is generated. The simu-lation is performed in terms of events, taking account ofindividual input thresholds.Both the transitions and the events are stored in differentdata structures. The transitions use a list-type structure,storing timing parameters τx and t0 where x indicates rise orfall transition type. The events a use queue-type structure,storing only the time instant (E) when the event takes place.Every event is associated to a gate input that is included inthe data structure that holds the circuit netlist, and also tothe transition that caused the event3.2 Simulation AlgorithmIn Figure 4, it can be seen the basic steps of the pro-posed simulation algorithm. Every step performs the tasksthat are described below.The task of the first step is to get the first event from theevent queue, and get all associated data from the class rela-tions. These data are the gate and the gate input where eventoccurs and the transition that produces it.In the second step, the output transition is calculatedusing the DDM directly.When the output transition is calculated and generated,the algorithm enters a loop where two tasks must be per-formed. First, it must generate all events associated to thistransition and, second, it must evaluate the presence of iner-tial effect in every gate input. This process begins findingout the associated gate input to the current transitionthrough the relations between the transition class and gateinput class. For each gate input, the Ej event is calculatedwhich will be the j-th event associated to this gate input.NetlistLineTransitionEventGateInputNextPrevNextPrev{ordered}producesFigure 2. HALOTIS class diagramE1VT22VT31VHVLE2 E3VT13123VT13123VT22123VT31123Figure 3. A transition in signal “out” and it’sassociated eventsTransition Event Gate Gate input Thresholdτf, t0E1 G2 2 VT22E2 G3 1 VT31E3 G1 3 VT13τf, t0G1G2G3OutOuttGet first event from event queueFor the associated transition, calculatethe output transition using DDM modelGet next associated gate inputCalculate Ej eventEj-1>EjDelete Ej-1 Insert EjIs there anothergate input?Yes NoYesGet next eventNoFigure 4. Simulation algorithmF.A.F.A. F.A. F.A. F.A.F.A. F.A. F.A. F.A.F.A. F.A. F.A. F.A. 000a3 a2 a1 a0a3 a2 a1 a0a3 a2 a1 a0a3 a2 a1 a0b0b1b2b30s3 s2 s1 s0s4s5s6s7ai bicici+1sici+1aibicisiFigure 5. 4x4 Multiplier circuitThis event is compared with the previous event in this sameinput (Ej-1). If the new event takes place after the previousone, it is inserted in the event queue, otherwise, the previ-ous event is removed from the queue.4. Simulation ResultsFigure 5 shows a 4x4 bit multiplier circuit, whose simu-lation results will serve to verify HALOTIS. The circuit hasbeen designed in a 0.6µm CMOS technology.Figure 6 includes the simulation results of the inputsequence 0x0, 7x7, 5xA, Ex6, FxF obtained with HSPICE,HALOTIS-DDM and HALOTIS-CDM. HALOTIS-DDMis the simulator HALOTIS incorporating DDM, whileHALOTIS-CDM incorporates a conventional delay model,that is, without degradation effect. This is neccesary tocompare different types of simulation results.It is observed that HALOTIS-DDM and HSPICE resultsare very similar, while HALOTIS-CDM results showsmuch more output transitions than the others. This is due tothe exclusion of degradation effect, making the glitchesgenerated in the circuit being propagated to the output. Inboth HSPICE and HALOTIS-DDM, these glitches are deg-radated and, finally, rejected from the output.Figure 7 shows the simulation results of the 0x0, FxF,0x0, FxF, 0x0 multiplication sequence. From the point of0 5 10 15 20 25t (ns)s7s6s5s4s3s2s1s0AxB 0x0 7x7 5xA Ex6 FxF0 5 10 15 20 25t (ns)s7s6s5s4s3s2s1s0AxB 0x0 7x7 5xA Ex6 FxF0 5 10 15 20 25t (ns)s7s6s5s4s3s2s1s0AxB 0x0 7x7 5xA Ex6 FxFFigure 6. Simulation results of the 0x0, 7x7, 5xA,Ex6, FxF multiplication sequence with a) HSPICE,b) HALOTIS-DDM, c) HALOTIS-CDMa)b)c)Figure 7. Simulation results of the 0x0, FxF, 0x0,FxF multiplication sequence with a) HSPICE, b)HALOTIS-DDM, c) HALOTIS-CDM0 5 10 15 20 25s7s6s5s4s3s2s1s0AxB 0x0 FxF 0x0 FxF 0x0t (ns)0 5 10 15 20 25s7s6s5s4s3s2s1s0AxB 0x0 FxF 0x0 FxF 0x0t (ns)0 5 10 15 20 25s7s6s5s4s3s2s1s0AxB 0x0 FxF 0x0 FxF 0x0t (ns)a)b)c)view of the waveforms, the conclusions of the analysis arethe same than those explained in the previous case.A very interesting aspect of the results are concerningthe switching activity. Table 1 includes the measurement ofthe switching activity for HALOTIS-DDM and HALOTIS-CDM. It is very significative that the use of conventionaldelay models can produce an overestimation in switchingactivity up to the 40%.On the other hand, Table 2 includes the CPU times fordifferent kinds of simulation. As expected, HALOTIS isbetween 2 or 3 orders of magnitude faster than HSPICE.Another interesting result is that HALOTIS-DDM is fasterthan HALOTIS-CDM due to the reduced switching activityof the former.5. ConclusionsBecause of the features of Inertial and DegradationDelay Model (IDDM) for CMOS gates, their inclusion incurrent logic-timing simulators is a very complex task. Forthis reason, we have developed HALOTIS, a new timing-logic simulation tool. The most relevant aspects of HALO-TIS are the novel way to deal with of stimuli and the simu-lation algorithm, able to include the IDDM. Thus,HALOTIS can provide high accuracy simulation results,very similar to those provided by electrical simulators asHSPICE, reducing up to three orders of magnitude the CPUsimulation time. When comparing to conventionals event-driven techniques, the results are more accurate when con-sidering the propagation and degradation of glitches andnarrow pulses, even spending less simulation time, sinceHALOTIS contemplates a reduction in the switching activ-ity due to the inclusion of the inertial and degradationeffects.6. References[1] L. Bisdounis, S. Nikolaidis, O. Koufopavlou. “AnalyticalTransient Response and Propagation Delay Evaluationof the CMOS Inverter for Short-Channel Devices”. IEEEJ. of Solid-State Circ. pp. 302-306. Vol. 33, no. 2, Feb.1998.[2] J.M. Daga, D. Auvergne. “A Comprehensive Delay MacroModeling for Submicrometer CMOS Logics”. IEEE J. ofSolid State Circuits. Vol. 34, No. 1, Jan. 1999.[3] A.I. Kayssi, K.A. Sakallah, T.N. Mudge. “The Impact ofSignal Transition Time on Path Delay Computation”.IEEE Trans. on Circuits and Systems-II: Analog andDigital Signal Processing, Vol. 40, No. 5, pp. 302-309,May 1993.[4] D. Auvergne, N. Azemard, D. Deschacht, M. Robert. “InputWaveform Slope Effects in CMOS Delays”. IEEE J. ofSolid-State Circ., Vol. 25, No. 6, pp. 1588-1590. Dec.1990[5] E. Melcher, W. Röthig, M. Dana. “Multiple Input Transitionsin CMOS Gates”. Microprocessing and Micro-programming 35 (1992) pp. 683-690. North Holland.[6] C. Metra, M. Favalli, B. Riccò. “Glitch power dissipationmodel”. In Proc. PATMOS'95. pp. 175-189[7] M. Eisele, J. Berthold. “Dynamic Gate Delay Modeling forAccurate Estimation of Glitch Powe at Logic Level”. InProc. PATMOS'95. pp. 190-201.[8] S. H. Unger. “The essence of logic circuits”. Ed. Prentice-Hall International, Inc. 1989[9] L.R. Marino. “General Theory of Metastable Operation”.IEEE Trans. on Computers, C-30 n.2, pp. 107-115, Feb.1981.[10] L. Kleeman, A. Cantoni. “Metastable Behavior in DigitalSystems”, IEEE Design and Test of Computers, vol. 4.Dec. 1987[11] L.M. Reyneri, L.M. del Corso, B. Sacco. “OscillatoryMetastability in Homogeneous and InhomogeneousFlip-flops”. IEEE J. of Solid-State Circ. Vol.25. n.1. Feb.1990.[12] J. Calvo, M. Valencia, J.L. Huertas. “Metastable Operation inRS Flip-flops”. Int. J. Electronics, Vol. 70 n.6. 1991.[13] D. Rabe, B. Fiuczynski, L. Kruse, A. Welslau, W. Nebel.“Comparison of Different Gate Level Glitch Models”. InProc. PATMOS'96. pp. 167-176.[14] J. Juan-Chico, P. Ruiz-de-Clavijo, M.J. Bellido, A.J. Acosta,M. Valencia. “Inertial and degradation delay model forCMOS logic gates”. In Proc. IEEE InternationalSymposium on Circuits and Systems (ISCAS) 2000, pp.I-459-462, Geneva, May 2000.[15] J. Juan-Chico, P. Ruiz-de-Clavijo, M.J. Bellido, A.J. Acosta,M. Valencia: “Degradation delay model extension toCMOS gates”. In Proc. Power and Timing Modelling,Optimization and Simulation (PATMOS) 2000, pp. 149-158, Sept. 2000.[16] J. Juan-Chico, M.J. Bellido, A.J. Acosta, A. Barriga, M.Valencia. “Delay degradation effect in submicronicCMOS inverters”. In Proc. PATMOS'97. pp. 215-224.Louvain-la-Neuve, Belgium, 1997.[17] M.J. Bellido, J. Juan-Chico, A.J. Acosta, M. Valencia and J.L.Huertas. “Logical modelling of delay degradation effectin static CMOS gates”. IEE Proceedings, Circuits,Devices and Systems, Vol. 147, No. 2, pp. 107-117. April2000. Table 1. HALOTIS simulation results statisticsSequenceEvents Filtered eventsHALOTIS-DDMHALOTIS-CDMOverst. CDM(%)HALOTIS-DDMHALOTIS-CDM0x0, 7x7, 5xA, Ex6, FxF 959 1411 47 27 10x0, FxF, 0x0, FxF, ... 1312 1992 52 66 6 Table 2. CPU time in seconds for simulations.Sequence HSPICE HALOTIS-DDMHALOTIS-CDM0x0, 7x7, 5xA, Ex6, FxF 112.9 0.39 0.550x0, FxF, 0x0, FxF, ... 123.0 0.48 0.76

HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model

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HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model

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