Service Differentiated and Adaptive CSMA/CA over IEEE 802.15.4 for Cyber-Physical Systems

Cyber-Physical Systems (CPS) that collect, exchange, manage information, and coordinate actions are an integral part of the Smart Grid. In addition, Quality of Service (QoS) provisioning in CPS, especially in the wireless sensor/actuator networks, plays an essential role in Smart Grid applications. IEEE 802.15.4, which is one of the most widely used communication protocols in this area, still needs to be improved to meet multiple QoS requirements. This is because IEEE 802.15.4 slotted Carrier Sense Multiple Access/Collision Avoidance (CSMA/CA) employs static parameter configuration without supporting differentiated services and network self-adaptivity. To address this issue, this paper proposes a priority-based Service Differentiated and Adaptive CSMA/CA (SDA-CSMA/CA) algorithm to provide differentiated QoS for various Smart Grid applications as well as dynamically initialize backoff exponent according to traffic conditions. Simulation results demonstrate that the proposed SDA-CSMA/CA scheme significantly outperforms the IEEE 802.15.4 slotted CSMA/CA in terms of effective data rate, packet loss rate, and average delay

Polysaccharides from the root of Angelica sinensis promotes hematopoiesis and thrombopoiesis through the PI3K/AKT pathway

<p>Abstract</p> <p>Background</p> <p>Dozens of Traditional Chinese Medicine (TCM) formulas have been used for promotion of "blood production" for centuries, and we are interested in developing novel thrombopoietic medicines from these TCMs. Our previous studies have demonstrated the hematopoietic effects of DangGui BuXue Tong (DBT), a formula composed of <it>Radix Angelicae Sinensis </it>and <it>Radix Astragali </it>in animal and cellular models. As a step further to identify and characterize the active chemical components of DBT, we tested the hematopoietic and particularly, thrombopoietic effects of polysaccharide-enriched fractions from the root of <it>Radix Angelicae Sinensis </it>(APS) in this study.</p> <p>Methods</p> <p>A myelosuppression mouse model was treated with APS (10 mg/kg/day). Peripheral blood cells from APS, thrombopoietin and vehicle-treated samples were then counted at different time-points. Using the colony-forming unit (CFU) assays, we determined the effects of APS on the proliferation and differentiation of hematopoietic stem/progenitor cells and megakaryocytic lineages. Using a megakaryocytic cell line M-07e as model, we analyzed the cellular apoptosis progression with and without APS treatment by Annexin V, Mitochondrial Membrane Potential and Caspase 3 assays. Last, the anti-apoptotic effect of APS on cells treated with Ly294002, a Phosphatidylinositol 3-Kinse inhibitor (PI3K) was also tested.</p> <p>Results</p> <p>In animal models, APS significantly enhanced not only the recovery of platelets, other blood cells and their progenitor cells, but also the formation of Colony Forming Unit (CFU). In M-07e cells, we observed the anti-apoptotic effect of APS. Treatment by Ly294002 alone increased the percentage of cells undergoing apoptosis. However, addition of APS to Ly294002-treated cells significantly reduced the percentage of cells undergoing apoptosis.</p> <p>Conclusions</p> <p>APS promotes hematopoiesis and thrombopoiesis in the mouse model. This effect likely resulted from the anti-apoptosis activity of APS and is likely to involve the PI3K/AKT pathway.</p

Pathological Complete Response Following Neoadjuvant Tislelizumab Monotherapy in Treatment-Naive Locally Advanced, MMR-Deficient/MSI-High Ascending Colon Cancer: A Case Report

Although recent trials started the use of neoadjuvant immunotherapy (NIT) in instability-high (MSI-H) or mismatch repair deficient (dMMR) early-stage or locally advanced colorectal cancer (LACRC), little data on the treatment strategy of NIT has been shown, and whether the tirelizumab mono-immune checkpoint inhibitor (ICI) can be used as NIT for patients with LACRC has not been reported as yet. In this study we report on a locally advanced ascending colon cancer case with a history of incomplete intestinal obstruction which achieved a pathologic complete response (pCR) after treated with Tirelizumab as NIT. A 32-year-old man was diagnosed with locally advanced ascending colon cancer with MSI-H and dMMR. An incomplete intestinal obstruction accompanied with hyperpyrexia occurred unexpectedly and was eased by symptomatic treatment. There was no peritonitis or other acute complications. NIT (three cycles of Tirelizumab) was suggested by the MDT board and partial response was achieved according to CT scanning, and pCR was further revealed by postoperative pathology. A ctDNA clearance confirmed the R0 resection and some immunotherapy related predictors were also detected using the NGS method. Our case study contributes to the evidence on the feasibility, efficacy, and safety of f Tirelizumab as a mono ICI for an optional neoadjuvant therapy in patients with MSI-H/dMMR LACRC

Reconfigurable electronics by disassembling and reassembling van der Waals heterostructures.

Van der Waals heterostructures (vdWHs) have attracted tremendous interest owing to the ability to assemble diverse building blocks without the constraints of lattice matching and processing compatibility. However, once assembled, the fabricated vdWHs can hardly be separated into individual building blocks for further manipulation, mainly due to technical difficulties in the disassembling process. Here, we show a method to disassemble the as-fabricated vdWHs into individual building blocks, which can be further reassembled into new vdWHs with different device functionalities. With this technique, we demonstrate reconfigurable transistors from n-type to p-type and back-gate to dual-gate structures through re-stacking. Furthermore, reconfigurable device behaviors from floating gate memory to Schottky diode and reconfigurable anisotropic Raman behaviors have been obtained through layer re-sequencing and re-twisting, respectively. Our results could lead to a reverse engineering concept of disassembled vdWHs electronics in parallel with state-of-the-art vdWHs electronics, offering a general method for multi-functional pluggable electronics and optoelectronics with limited material building blocks

Reconfigurable electronics by disassembling and reassembling van der Waals heterostructures.

Van der Waals heterostructures (vdWHs) have attracted tremendous interest owing to the ability to assemble diverse building blocks without the constraints of lattice matching and processing compatibility. However, once assembled, the fabricated vdWHs can hardly be separated into individual building blocks for further manipulation, mainly due to technical difficulties in the disassembling process. Here, we show a method to disassemble the as-fabricated vdWHs into individual building blocks, which can be further reassembled into new vdWHs with different device functionalities. With this technique, we demonstrate reconfigurable transistors from n-type to p-type and back-gate to dual-gate structures through re-stacking. Furthermore, reconfigurable device behaviors from floating gate memory to Schottky diode and reconfigurable anisotropic Raman behaviors have been obtained through layer re-sequencing and re-twisting, respectively. Our results could lead to a reverse engineering concept of disassembled vdWHs electronics in parallel with state-of-the-art vdWHs electronics, offering a general method for multi-functional pluggable electronics and optoelectronics with limited material building blocks

Mobility Enhancement of Strained MoS₂ Transistor on Flat Substrate

Strain engineering has been proposed as a promising method to boost the carrier mobility of two-dimensional (2D) semiconductors. However, state-of-the-art straining approaches are largely based on putting 2D semiconductors on flexible substrates or rough substrate with nanostructures (e.g., nanoparticles, nanorods, ripples), where the observed mobility change is not only dependent on channel strain but could be impacted by the change of dielectric environment as well as rough interface scattering. Therefore, it remains an open question whether the pure lattice strain could improve the carrier mobilities of 2D semiconductors, limiting the achievement of high-performance 2D transistors. Here, we report a strain engineering approach to fabricate highly strained MoS2 transistors on a flat substrate. By mechanically laminating a prefabricated MoS2 transistor onto a custom-designed trench structure on flat substrate, well-controlled strain can be uniformly generated across the 2D channel. In the meantime, the substrate and the back-gate dielectric layer remain flat without any roughness-induced scattering effect or variation of the dielectric environment. Based on this technique, we demonstrate the MoS2 electron mobility could be enhanced by tension strain and decreased by compression strain, consistent with theoretical predictions. The highest mobility enhancement is 152% for monolayer MoS2 and 64% for bilayer MoS2 transistors, comparable to that of a silicon device. Our method not only provides a compatible approach to uniformly strain the layered semiconductors on flat and solid substrate but also demonstrates an effective method to boost the carrier mobilities of 2D transistors

High-density vertical sidewall MoS2 transistors through T-shape vertical lamination.

Vertical transistors, in which the source and drain are aligned vertically and the current flow is normal to the wafer surface, have attracted considerable attention recently. However, the realization of high-density vertical transistors is challenging, and could be largely attributed to the incompatibility between vertical structures and conventional lateral fabrication processes. Here we report a T-shape lamination approach for realizing high-density vertical sidewall transistors, where lateral transistors could be pre-fabricated on planar substrates first and then laminated onto vertical substrates using T-shape stamps, hence overcoming the incompatibility between planar processes and vertical structures. Based on this technique, we vertically stacked 60 MoS2 transistors within a small vertical footprint, corresponding to a device density over 108 cm-2. Furthermore, we demonstrate two approaches for scalable fabrication of vertical sidewall transistor arrays, including simultaneous lamination onto multiple vertical substrates, as well as on the same vertical substrate using multi-cycle layer-by-layer laminations

Wafer-scale and universal van der Waals metal semiconductor contact

Van der Waals (vdW) metallic contacts have been demonstrated as a promising approach to reduce the contact resistance and minimize the Fermi level pinning at the interface of two-dimensional (2D) semiconductors. However, only a limited number of metals can be mechanically peeled and laminated to fabricate vdW contacts, and the required manual transfer process is not scalable. Here, we report a wafer-scale and universal vdW metal integration strategy readily applicable to a wide range of metals and semiconductors. By utilizing a thermally decomposable polymer as the buffer layer, different metals were directly deposited without damaging the underlying 2D semiconductor channels. The polymer buffer could be dry-removed through thermal annealing. With this technique, various metals could be vdW integrated as the contact of 2D transistors, including Ag, Al, Ti, Cr, Ni, Cu, Co, Au, Pd. Finally, we demonstrate that this vdW integration strategy can be extended to bulk semiconductors with reduced Fermi level pinning effect