Search Process Checklist

The Search Process Checklist is a tool that is used in instructional sessions with nurses in reference to evidence-based practice and literature searching. It is intended as a reference handout. It is under a creative commons license. If you would like a version that can be rebranded for your organization to use, please contact the author for an editable version

VCU Health Nursing Inquiry Process Diagram (version 2)

This diagram outlines the nursing inquiry process to help answer questions that arise in the clinical setting. The diagram further helps a nurse understand how to distinguish whether a situation calls for evidence-based practice, performance improvement or research. It also guides a nurse through clarifying the initial question, gathering the evidence, and through each step in the subsequent process

Parallel semiconductor device simulation: from power to 'atomistic' devices

This paper discusses various aspects of the parallel simulation of semiconductor devices on mesh connected MIMD platforms with distributed memory and a message passing programming paradigm. We describe the spatial domain decomposition approach adopted in the simulation of various devices, the generation of structured topologically rectangular 2D and 3D finite element grids and the optimisation of their partitioning using simulated annealing techniques. The development of efficient and scalable parallel solvers is a central issue of parallel simulations and the design of parallel SOR, conjugate gradient and multigrid solvers is discussed. The domain decomposition approach is illustrated in examples ranging from `atomistic' simulation of decanano MOSFETs to simulation of power IGBTs rated for 1000 V

RTS amplitudes in decanano n-MOSFETs with conventional and high-k gate stacks

Low frequency (LF) noise in MOSFETs has been a topic of interest to both academia and industry in recent years. It is becoming a major concern for analogue circuit performance, DRAM operation, and will eventually impact critically upon the reliability of digital logic especially as devices continue to scale towards nano dimensions. Random telegraph signals (RTS) caused by the capture and emission of carriers in traps at the Si/SiO/sub 2/ interface have been posited as a major component of low frequency noise in semiconductor devices. The change in the drain current associated with trapping events in defect states is usually referred to as the RTS amplitude. The magnitude of the RTS amplitude is largest in the subthreshold regime at lower gate voltages and is reduced in the strong inversion regime as mobile charge in the inversion layer increasingly screens out the electrostatic influence of the trapped charge. We study the magnitude of the RTS amplitudes in nano-CMOS devices with conventional and high- gate stacks. Traps at the front and back gate dielectric interfaces, as well as traps in the body of the dielectric are considered. The impact of poly gate depletion is also taken into account

Grid infrastructures for the electronics domain: requirements and early prototypes from an EPSRC pilot project

The fundamental challenges facing future electronics design is to address the decreasing – atomistic - scale of transistor devices and to understand and predict the impact and statistical variability these have on design of circuits and systems. The EPSRC pilot project “Meeting the Design Challenges of nanoCMOS Electronics” (nanoCMOS) which began in October 2006 has been funded to explore this space. This paper outlines the key requirements that need to be addressed for Grid technology to support the various research strands in this domain, and shows early prototypes demonstrating how these requirements are being addressed

PROBE-GK: Predictive Robust Estimation using Generalized Kernels

Many algorithms in computer vision and robotics make strong assumptions about uncertainty, and rely on the validity of these assumptions to produce accurate and consistent state estimates. In practice, dynamic environments may degrade sensor performance in predictable ways that cannot be captured with static uncertainty parameters. In this paper, we employ fast nonparametric Bayesian inference techniques to more accurately model sensor uncertainty. By setting a prior on observation uncertainty, we derive a predictive robust estimator, and show how our model can be learned from sample images, both with and without knowledge of the motion used to generate the data. We validate our approach through Monte Carlo simulations, and report significant improvements in localization accuracy relative to a fixed noise model in several settings, including on synthetic data, the KITTI dataset, and our own experimental platform.Comment: In Proceedings of the IEEE International Conference on Robotics and Automation (ICRA'16), Stockholm, Sweden, May 16-21, 201

A late-accelerating universe with no dark energy - and a finite-temperature big bang

Brane-world models offer the possibility of explaining the late acceleration of the universe via infra-red modifications to General Relativity, rather than a dark energy field. However, one also expects ultra-violet modifications to General Relativity, when high-energy stringy effects in the early universe begin to grow. We generalize the DGP brane-world model via an ultra-violet modification, in the form of a Gauss-Bonnet term in the bulk action. The combination of infra-red and ultra-violet modifications produces an intriguing cosmology. The DGP feature of late-time acceleration without dark energy is preserved, but there is an entirely new feature - there is no hot big bang in the early universe. The universe starts with finite density and pressure, from a "sudden" curvature singularity.Comment: revised title and minor improvements, additional references; to appear JCA

UTB SOI SRAM cell stability under the influence of intrinsic parameter fluctuation

Intrinsic parameter fluctuations steadily increases with CMOS technology scaling. Around the 90nm technology node, such fluctuations will eliminate much of the available noise margin in SRAM based on conventional MOSFETs. Ultra thin body (UTB) SOI MOSFETs are expected to replace conventional MOSFETs for integrated memory applications due to superior electrostatic integrity and better resistant to some of the sources of intrinsic parameter fluctuations. To fully realise the performance benefits of UTB SOI based SRAM cells a statistical circuit simulation methodology which can fully capture intrinsic parameter fluctuation information into the compact model is developed. The impact on 6T SRAM static noise margin characteristics of discrete random dopants in the source/drain regions and body-thickness variations has been investigated for well scaled devices with physical channel length in the range of 10nm to 5nm. A comparison with the behaviour of a 6T SRAM based on a conventional 35nm MOSFET is also presented

Impact of random dopant induced fluctuations on sub-15nm UTB SOI 6T SRAM cells

The CMOS scaling increases the impact of intrinsic parameter fluctuation on the yield and functionality of SRAM. A statistical circuit simulation framework which can fully capture intrinsic parameter fluctuation information into the compact model has been developed. The impact of discrete random dopants in the source and drain regions on 6T SRAM cells has been investigated for well scaled ultra thin body (UTB) SOI MOSFETs with physical channel length in the range of 10nm to 5nm