The CMOS scaling increases the impact of intrinsic parameter fluctuation on the yield and functionality of SRAM. A statistical circuit simulation framework which can fully capture intrinsic parameter fluctuation information into the compact model has been developed. The impact of discrete random dopants in the source and drain regions on 6T SRAM cells has been investigated for well scaled ultra thin body (UTB) SOI MOSFETs with physical channel length in the range of 10nm to 5nm

Asenov, A.

Brown, A.R.

Cheng, B.

Roy, S.

Samsudin, K.

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2005 IEEE International SOI ConferenceImpact of Random Dopant Induced Fluctuations on Sub-l5nm UTB SOI 6T SRAM CellsK. Samsudin*, B. Cheng, A. R. Brown, S. Roy and A. AsenovDevice Modelling Group, Dept. of Electronics and Electrical EngineeringUniversity of Glasgow, Glasgow G12 8LT, Scotland, UK.*Email: K.Samsudin@elec.gla.ac.uk, Tel: +44 141 330 2964Abstract: The CMOS scaling increases the impact ofintrinsic parameter fluctuation on the yield and function-ality of SRAM. A statistical circuit simulation frame-work which can fully capture intrinsic parameter fluc-tuation information into the compact model has beendeveloped. The impact of discrete random dopants inthe source and drain regions on 6T SRAM cells has beeninvestigated for well scaled Ultra Thin Body (UTB) SOIMOSFETs with physical channel length in the range of10nm to 5nm.Introduction: Around the 90nm technology node, in-trinsic parameter fluctuations will drasticaly reduce thenoise margin and overall speed in SRAM based on con-ventional MOSFETs [1]. SRAMs based on UTB SOIMOSFETs will outperform the conventional MOSFETsone due to superior electrostatic integrity, significantreduction of collective junction capacitance on the bit-line and improved intrinsic parameter fluctuations. Al-though UTB device can operate without dopant withinthe channel region there are necessarily discrete randomdopants in the source/drain regions that will introducefluctuations in the effective channel length and accessresistance at nanoscale dimensions.Simulation Methodology: The physical parameters ofcarefully scaled UTB SOI MOSFETs are summarised inTable 1. In order to capture statistical variation associ-ated with the discrete random dopants in the source anddrain regions as illustrated in Fig. 1, an ensemble of 200macroscopically identical, but microscopically differentdevices is created and simulated using the Glasgow 3D'atomistic' drift diffusion simulator [2].An improved two-stage statistical parameter extractionmethodology [3] is employed to capture all devicefluctuation information obtained from the 3D 'atom-istic' simulator into a representative set of BSIMSOI-FD compact models library. Fig. 2(a) illustrates thequality of BSIMSOI extraction from 3 extreme casesof the physically simulated ID-VG characteristics. Thestatic transfer characteristics of the 6T SRAM cells isdepicted in Fig. 2(b). Transistors in the SRAM circuitare randomly selected from the compact models libraryduring SPICE simulation of 1, 2 and 3 cell ratio.Results and Discussions: Figure 3 illustrates the dis-tribution of the static noise margin (SNM) due to dis-crete random doping for SRAM cells with differentcell ratios, corresponding to each channel length beinginvestigated here. It clearly follows the expected trendthat increasing cell ratio improves cell stability althoughit delivers less improvement of the SNM with smallerchannel length. The SRAMs based on 5nm transistorscould not achieve the required yield even at cell ratio 3,while 10nm and 7.5nm requires at least a cell ratio of2 and 3 respectively. Typical write operation stabilityconsidering quasi-static operation is shown in Table 3.The relative read operation speed of the different cells isobtained by measuring the discharge time for the bitlineas shown in Fig. 4 and Table 4. As a measure of thewrite times, the worst-case flip time of the bitlines wasrecorded as shown in Table 5. Roughly the discreterandom dopants will cause 40% performance differencefor read operation and less then 5% difference for writeoperation.Conclusions: UTB SOI MOSFETs could extend thebenefits of SRAM scaling beyond the 65nm technologynode [5]. However, novel device architectures such asDouble Gate MOSFETs are required after the 10nmchannel length mark. It is important that each potentialsources of intrinsic parameter fluctuation is carefullystudied to fully map their impact on the correspondingSRAM cell generations.References[1 ] B. Cheng, S. Roy, and A. Asenov, "The impact of randomdoping effects on CMOS SRAM cell," in ESSCIRC, 2004.[2] A. R. Brown, F. Adamu-Lema, and A. Asenov, "Intrinsicparameter fluctuations in nanometre scale thin-body SOIdevices introduced by interface roughness," Superlatticesand Microstructures, vol. 34, pp. 283-291, 2003.[3] K. Samsudin, B. Cheng, et al., "Impact of body thicknessfluctuation in nanometre scale UTB SOI MOSFETs onSRAM cell functionality," in 6th European Conference onUltimate Integration of Silicon, (Bologna, Italy), pp. 45-48, April 2005.[4] P. Stolk, H. Tuinhout, et al., "CMOS device optimizationfor mixed-signal technologies," Tech. Digest IEDM,pp.215-218,2001.[5] "International Technology Roadmap for Semiconduc-tors," 2003.0-7803-9212-41051$20.00 ©2005 IEEE 612005 IEEE International SOI ConferenceChannel Length (nm) 10 7.5 5Gate Oxide Thickness, To, (nm) 0.67 0.5 0.33Body Thickness, T,i(nm) 2.5 2.25 2.0Buried Oxide Thickness, TN,0x(nm) 50Channel Doping, N0 (cm-') lel4source-drain Doping, NS/j, (cm-') 2e20Table 1: Generic device parameters considered., *1Cell Ratio Mean, p(mV) SD, a(mV) a/p(%)1 542 17 3.2lOnm 2 586 18 3.13 612 19 3.1473 27 5.77.5nm 2 512 26 5.13 534 27 5.01 451 57 12.6Snm 2 485 58 12.03 505 56 0.11Table 3: Switch Point Voltage distributions . The writeoperation stability could be measured by switch point voltagewhich is defined as the bit line voltage that will cause data tobegin to change under a write operation.Fig. 1: Location of discrete random dopants in thesource/drain regions and corresponding variation of effectivechannel length in the silicon body of a 10nm UTB SOIMOSFET.-8~~~~~~~~~~~~~~~~~~~-lo' /.BSIMSOOI(V0-000)0 02 04 06 08 0010203040506070806(V) 0,1 X(V)(a)151050, 15v 10Slo1?5U-0151050(b)Fig. 2: (a) Compact model calibration of gate characteristicsfor 3 extreme fluctuation cases of lOnm channel length.All characteristics are from nMOSFET UTB SOI. (b) Statictransfer characteristics of 200 statistical 6T SRAM cellsutilising I Onm UTB MOSFET with a cell ratio of 1.20 - Onm1510-O- t 7.5nmL 15Cy 10U.2015 Cell RatioI 0 L ,_ S1/1E~~~~~~~~~~2/10.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14SNM (V)1.0 1.5 2.0Read Time (ns)2.5 3.0Fig. 4: SRAM read discharge time distribution.Cell Ratio Mean, p(ns) SD, a(ns) a/,ui(%)1 1.28 0.073 5.71 Onm 2 0.91 0.053 5.83 0.79 0.048 6.21 1.65 0.196 11.87.5nm 2 1.14 0.129 11.23 0.98 0.114 11.61 2.09 0.366 17.5Snm 2 1.49 0.299 20.03 1.28 0.257 20.1Table 4: SRAM read discharge time distribution. The readdischarge time is measured when one of the bitlines is reducedto half of the supply voltage after the wordline is raised.Fig. 3: Static Noise Margin Distributions.Cell Ratio Mean, g(mV) SD, cr(mV) a/l(%)1 81.9 10.1 12.31 Onm 2 115.4 7.8 6.73 132.9 7.1 5.31 70.2 11.5 16.57.5nm 2 89.8 12.3 13.73 106.2 10.7 10.11 34.0 22.1 65.0Snm 2 37.5 23.9 63.73 53.8 23.5 43.6Table 2: Static Noise Margin distributions during readoperation. The Static Noise Margin (SNM) is the minimumDC noise voltage needed to flip the cell state. As a guideline,u-6a is required to exceed 4% of the supply voltage to achieve90% yield on IMbit SRAM [4].Cell Ratio Mean, AL(ps) SD, ca(ps) c/M(%)1 231.4 3.91 1.69I Onm 2 234.0 4.29 1.833 236.1 4.66 1.971 241.8 7.77 3.217.5nn 2 244.8 8.46 3.463 247.3 9.30 3.761 255.8 21.82 8.535nm 2 260.3 25.30 9.723 265.0 29.91 11.29Table 5: SRAM Write time distribution. The flip time wasmeasured from the time the wordline was raised after placingan opposite value on the bitlines to when the latter of the twostorage nodes reached 90% of its final value.62110nm7.5nm'^ -5nm Cell Ratio2/1

11.29 Table 5: SRAM Write time distribution. The flip time was measured from the time the wordline was raised after placing an opposite value on the bitlines to when the latter ofthe two storage nodes reached 90% ofits final value.

43.6 Table 2: Static Noise Margin distributions during read operation. The Static Noise Margin (SNM) is the minimum DC noise voltage needed to flip the cell state. As a guideline, u-6a is required to exceed 4% ofthe supply voltage to achieve

CMOS device optimization for mixed-signal technologies,&quot;

Fig. 4: SRAM read discharge time distribution. Cell Ratio Mean, p(ns) SD,

Table 4: SRAM read discharge time distribution. The read discharge time is measured when one ofthe bitlines is reduced to halfofthe supply voltage after the wordline is raised.

The impact ofrandom doping effects on CMOS SRAM cell,&quot; in ESSCIRC,

Impact of random dopant induced fluctuations on sub-15nm UTB SOI 6T SRAM cells

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Impact of random dopant induced fluctuations on sub-15nm UTB SOI 6T SRAM cells

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