Integrating 'atomistic', intrinsic parameter fluctuations into compact model circuit analysis

MOSFET parameter fluctuations, resulting from the 'atomistic' granular nature of matter, are predicted to be a critical roadblock to the scaling of devices in future electronic systems. A methodology is presented which allows compact model based circuit analysis tools to exploit the results of 'atomistic' device simulation, allowing investigation of the effects of such fluctuations on circuits and systems. The methodology is applied to a CMOS inverter, ring oscillator, and analogue NMOS current mirror as simple initial examples of its efficacy

Grid infrastructures for the electronics domain: requirements and early prototypes from an EPSRC pilot project

The fundamental challenges facing future electronics design is to address the decreasing – atomistic - scale of transistor devices and to understand and predict the impact and statistical variability these have on design of circuits and systems. The EPSRC pilot project “Meeting the Design Challenges of nanoCMOS Electronics” (nanoCMOS) which began in October 2006 has been funded to explore this space. This paper outlines the key requirements that need to be addressed for Grid technology to support the various research strands in this domain, and shows early prototypes demonstrating how these requirements are being addressed

Integrated atomistic process and device simulation of decananometre MOSFETs

In this paper we present a methodology for the integrated atomistic process and device simulation of decananometre MOSFETs. The atomistic process simulations were carried out using the kinetic Monte Carlo process simulator DADOS, which is now integrated into the Synopsys 3D process and device simulation suite Taurus. The device simulations were performed using the Glasgow 3D statistical atomistic simulator, which incorporates density gradient quantum corrections. The overall methodology is illustrated in the atomistic process and device simulation of a well behaved 35 nm physical gate length MOSFET reported by Toshiba

Three levels of metric for evaluating wayfinding

Three levels of virtual environment (VE) metric are proposed, based on: (1) users’ task performance (time taken, distance traveled and number of errors made), (2) physical behavior (locomotion, looking around, and time and error classification), and (3) decision making (i.e., cognitive) rationale (think aloud, interview and questionnaire). Examples of the use of these metrics are drawn from a detailed review of research into VE wayfinding. A case study from research into the fidelity that is required for efficient VE wayfinding is presented, showing the unsuitability in some circumstances of common metrics of task performance such as time and distance, and the benefits to be gained by making fine-grained analyses of users’ behavior. Taken as a whole, the article highlights the range of techniques that have been successfully used to evaluate wayfinding and explains in detail how some of these techniques may be applied

Towards a grid-enabled simulation framework for nano-CMOS electronics

The electronics design industry is facing major challenges as transistors continue to decrease in size. The next generation of devices will be so small that the position of individual atoms will affect their behaviour. This will cause the transistors on a chip to have highly variable characteristics, which in turn will impact circuit and system design tools. The EPSRC project "Meeting the Design Challenges of Nano-CMOS Electronics" (Nana-CMOS) has been funded to explore this area. In this paper, we describe the distributed data-management and computing framework under development within Nano-CMOS. A key aspect of this framework is the need for robust and reliable security mechanisms that support distributed electronics design groups who wish to collaborate by sharing designs, simulations, workflows, datasets and computation resources. This paper presents the system design, and an early prototype of the project which has been useful in helping us to understand the benefits of such a grid infrastructure. In particular, we also present two typical use cases: user authentication, and execution of large-scale device simulations

Conversion from linear to circular polarization in FPGA

Context: Radio astronomical receivers are now expanding their frequency range to cover large (octave) fractional bandwidths for sensitivity and spectral flexibility, which makes the design of good analogue circular polarizers challenging. Better polarization purity requires a flatter phase response over increasingly wide bandwidth, which is most easily achieved with digital techniques. They offer the ability to form circular polarization with perfect polarization purity over arbitrarily wide fractional bandwidths, due to the ease of introducing a perfect quadrature phase shift. Further, the rapid improvements in field programmable gate arrays provide the high processing power, low cost, portability and reconfigurability needed to make practical the implementation of the formation of circular polarization digitally. Aims: Here we explore the performance of a circular polarizer implemented with digital techniques. Methods: We designed a digital circular polarizer in which the intermediate frequency signals from a receiver with native linear polarizations were sampled and converted to circular polarization. The frequency-dependent instrumental phase difference and gain scaling factors were determined using an injected noise signal and applied to the two linear polarizations to equalize the transfer characteristics of the two polarization channels. This equalization was performed in 512 frequency channels over a 512 MHz bandwidth. Circular polarization was formed by quadrature phase shifting and summing the equalized linear polarization signals. Results: We obtained polarization purity of -25 dB corresponding to a D-term of 0.06 over the whole bandwidth. Conclusions: This technique enables construction of broad-band radio astronomy receivers with native linear polarization to form circular polarization for VLBI.Comment: 11 pages 8 figure