MOSFET parameter fluctuations, resulting from the 'atomistic' granular nature of matter, are predicted to be a critical roadblock to the scaling of devices in future electronic systems. A methodology is presented which allows compact model based circuit analysis tools to exploit the results of 'atomistic' device simulation, allowing investigation of the effects of such fluctuations on circuits and systems. The methodology is applied to a CMOS inverter, ring oscillator, and analogue NMOS current mirror as simple initial examples of its efficacy

Asenov, A.

Cheng, B.J

Roy, G.

Roy, S.

English

Enlighten: Publications

Integrating 'atomistic', intrinsic parameter fluctuations into compact model circuit analysis

Cheng, B

Roy, S

Roy, G

Asenov, A

Enlighten

Integrating 'atomistic' intrinsic parameter fluctuations into compact model circuit analysis

      Cheng, B. J. and Roy, S. and Roy, G. and Asenov, A. (2003) Integrating 'atomistic', intrinsic parameter fluctuations into compact model circuit analysis. In, ESSDERC '03 : 33rd Conference on European Solid-State Device Research, 16-18 September 2003, pages pp. 437-440, Estoril, Portugal.      http://eprints.gla.ac.uk/2999/     Glasgow ePrints Service http://eprints.gla.ac.uk Integrating ‘atomistic’, intrinsic parameter - fluctuations into compact model circuit analysis. B. J. Cheng, S. Roy, 0. Roy, A. Asenov Device Modelling Group, Dept. o f  Electronics and Electrical Engineering University ofGlasgow5 Glasgow G I 2  SLT, Scotland, UK E-mail: asenov@elec.gla.ac.uk, Tel: +44 141 330 4792, Fax: +44 141 330 4907 Abstract: MOSFET parameter j7uctuations resulting from the ‘atomistic’ granular nature of malter. are predicted LO be a critical roadblock to the scaling of devices in .fitwe electronic systems. A methodologV is presented which alloivs compact model based circuit analysis rools to exploit the resirlts of ‘atomistic’ device simulalion, allowing investigation of the effects of such flucrualions on circuits and systems. The methodology is applied to a CMOS inverter, ring oscillator, and analogzre NMOS current mirror as simple initial examples oji ts  eflcacy. 1. Introduct ion There is considerable interest in intrinsic parameter fluctuations, caused by differences between otherwise macroscopically identical devices. A growing body of research i s  aimed at predicting the nature and magnitude o f  these ‘atomistic’ fluctuations due to, amongst other things, channel dopant number and position variation, oxide thickness variation, and line edge roughness [1,2]. Such fluctuations, for example i n  V, and wi l l  become steadily more pronounced as devices continue to scale. Although channel engineering methods have been presented as a short term palliative to restrain these fluctuations, some of the suggested solutions work against device short channel performance [3]. In circuits, parameter fluctuations ultimately lead to component mismatch and i t  i s  now widely realised that this problem may constitute a critical roadblock to the future performance and yield o f  both analogue and digital CMOS systems [4-61. Figure I clearly illustrates potential variations in a MOSFET due to random dopant position in the channel, source and drain, which may lead to such macroscopic fluctuations between devices. To create circuits which are efficient, and remain robust in the presence o f  intrinsic fluctuations, designers require niore than a worst-case estimate of fluctuation magnitude. Ideally, they require a device model which integrates naturally with present circuit analysis and electronic design automation (EDA) tools, and describes the effect of fluctuations over the whole range o f  device operation - i.e. a. set of compact models encompassing the appropriate physics o f  fluctuations, but reducing calculation time in an EDA tool by several orders o f  magnitude from that which would be required using present statistical, 3D device simulations. 437 2. ‘Atomistic’ Parameter Fluctuations In addition, intrinsic fluctuations resulting from the microscopic sources, may have a quite different nature to the traditional process related parameter fluctuations. For instance, differing channel dopant configurations wi l l  have a marked effect in sub-threshold, but relatively minor effect in saturation. Thus it is vital to have a methodolog specifically tailored to study the impact o f  different sources of intrinsic parameter fluctuations at circuit analysis level. This wi l l  allow us to investigate their effect, both separately and in combination, on the operation o f  circuits and systems. Fig. I Variation in  potential in a 35 nni MOSFET due to detailed positions of dopants i n  the chaniiel. source and drain. After [7]. In  order to better understand the implications of intrinsic ‘atomistic’ fluctuations independent o f  experimental process variations, an ensemble of 100 macroscopically identical, but microscopically different devices i s  created and simulated using the Glasgow ‘atomistic’ device simulator - which can correctly account for fluctuations introduced by discrete random doping distributions in the MOSFET channel, source and drain. The ensemble, which i s  used as source data for the rest o f  the extraction methodology, i s  based on the continuous doping profile o f  a 35 nm nMOSFET [SI, to which the simulator i s  rigorously calibrated. The details of this calibration are presented elsewhere [7]. Figure 2 shows typical l l j-V(; characteristics selected from the ensemble. V,,=O.SSV 1 E- ,iO B  I O  o 4vB(v)0 0 0  0 2  Fig. 2 Gate Characteristics from 100 macroscopically identical 35 nm nMOSFETs, obtained by ‘atomistic’ device simulation: We present, in section 3, an optimised methodology for extracting an ensemble of compact model parameters from statistical data produced by either experiment or device simulation.. In sections 4 and 5 we apply the methodology to analyse the performance of  foundational circuits for both digital and analogue applications. 3. Methodology The extraction -process is completed in two phases. Firstly, a complete set of BSIM3v3 model parameters is ’ extracted from the IV characteristics of a typical device with a continuous doping profile, and the ~ parameters divided into two’ groups: those ‘sensitive to ‘atomistic’ fluctuations, ’ and those insensitive to ‘atomistic’ fluctuations, which are fixed. after this phase. A combination.of local optimisation and a group extraction strategy is employed to extract the whole set of BSIM3v3 parameters using the Synopsys tool AURORA, focussing on those critica! to long channel behaviour, the threxhold voltage in the short channel regime, and drain-current response in the presence o f  high fields. Figures 3 and 4 show the quality of the BSIM3v3 parameter extraction results obtained for a typical 35 nm nMOSFET. The symbols are experimental results [8]. ~ . . .  . ~ - , ~  -._..__-__-___ __ ~- t- : .,,. ,--,. ;..I 0,000 0.200 0 . 4 0 0  0.600 0.800 .vg (volts1 ~. . Fig. 3 C&pact model calibration of gate cliaracteristics fol single 35 n n i  nMOSFET. - .  Fig. 4 Compact model calibration of drain characteristics for single 35 nm nMOSFET. From the device operation point of view, ‘atomistic’ dopant fluctuations in the channel, source and drain have three crucial effects. They cause significant drain current and sub-threshold slope variation in the weak inversion regime. They cause significant threshold voltage fluctuations, and they introduce some variation. Although the BSIM3v3 model does not directly consider these effects, it does introduce a number of empirical parameters to model different process conditions. Through careful parameter extraction, these parameters may be tuned to model the results of random doping effects. In principle, therefore, we can use BSIMh3 in a second phase of analysis by choosing a basis set of model parameters and modelling each member of the statistical ensemble with extracted values for these parameters. In this ,work, seven key BSIM3v3 model parameteware chosen to represent the effect of random discrete dopants; N, NfiC,<>?. K,T, ao, a,, a,, and d , h .  Figure 5 shows the variation of the three most important of these parameters. N , ,  is the effective channel doping, which will affect the model’s.threshold voltage, V,g will significantly affect the sub-threshold slope, and a,, directly affects the drain saturation voltage. . a0 - .  N d m ?  Fig. 5 Distributions of critical RSIM3.3 parameters over an ensemhle of 100 compact models calihrated to gate and drain characteristics oftlie devices in figure 4. 438 In this second phase of  extraction, parameters are tuned by first considering gate characteristics at IOW drain bias to match device threshold voltage and sub-threshold slope. Then the saturation regime i s  matched at high drain bias. The quality o f  the extracted compact models are equivalent to those o f  figure 3. Compared to other statistical compact modelling methodologies, the advantage of this two phase extraction strategy i s  that it can guarantee compact models which closely match the real ensemble of device results, whilst remaining feasible for the large ensemble sets necessary to obtain statistical circuit information. As an initial application o f  this methodology, we consider the distribution of propagation delays found in a simple inverter circuit subject to ‘atomistic’ fluctuations. One hundred circuits are simulated using HSPICE, with nMOSFETs from our ensemble, and continuously doped pMOSFETs calibrated from [SI. The pMOSFETs have width scaled x2.5 to match the nMOSFET drive current. Because of this symmetry, it can be seen that the modelled circuits wi l l  have a standard deviation 42 less than a complete simulation wi th ‘atomistic’ p and nMOSFETs. The input signal is from an ideal source with rise and fall times of 5 ps, and a load of 5 E. Inverter delay i s  .measured at 50% of supply voltage. Results are shown in figure 6, and i t  can be seen that in this, best possible case scenario, the circuit has an average propagation delay of 10.9 ps. The graph has a standard deviation of 1.3 ps. Delay (PS) Fig. 6 Distribution o f  circuit delays for inverter circuits incorporating nMOSFETs from ‘atomistic‘ eiiseoible. 4. Ring Oscillator The simplest CMOS circuit for timing tests is the ring osci\lator - and the circuit diagranl of a five stage oscillator is shown in figure 7. This circuit w i l l  give an indication of the performance o f  inverters in practice, when driven and loaded realistically. The inverters themselves are modelled as above, with interconnect capacitances assumed to be negligible. The results of circuit simulations on this system are shown in figure S. The average period of the whole five stage circuit i s  150.6 ps with (i = 4.2 ps. equivalent to a frequency o f  6.6 Chz with (i = 0.1 Chz, and a five stage delay of 75.3 ps with (i 2.1 pj. When accounting for more realistic inverter loads, and inore importantly, the finite /<,,, available in inverters as drivers, the single stage delay increases from 1 0 . 9 ~ s  to 15.1 ps. In addition the standard deviation of the delay, nai‘vely calculated from a single inverter stage (assuming independence o f  the variations of each inverter stage) as d 5 x  I .3 ps = 2.9 ps compares well with the actual variation of 2.1 ps. lk-, ‘i-, Fig. 7 Five-stage ring oscillator circuit. 140 145 150 155 160 Period (ps) Fig. 8 Distribution of minimum period for ring oscillator incorporating nMOSFETs from ’atomistic‘ ensemble. - 0 2 4 6 8 I O  12 Power supply variation (%) Fig. 9 Distribution o f  circuit delays for inverter circuits incorporating nMOSFETs from ‘atomistic’ ensemble. Deviations i n  propagation delays due to ‘atomistic‘ effects are modest. This i s  as expected, not only because the averaging effect o f  the ring oscillator stages, but also because the period is substantially dependant on drive current, which, due to screening in strong inversion, i s  relatively resistant to ‘atomistic’ fluctuations. It i s  emphasised in figure 9, which shows the standard deviation in period caused by power supply instability. ‘Atomistic’ ring oscillator fluctuations for 35 nm nMOSFETs are o f  the same order as fluctuations caused by a 5% supply instability. A14 5. Current  Mir ror  To demonstrate the effects of ‘atomistic’ fluctuations in a simple analogue circuit, a four nMOSFET transistor cascode current mirror, shown in figure IO, is chosen. mismatch distribution between /,/and I,,,, is spread from due to random dopants. 6.  Conclusions I -40% to +40%, reflecting a large threshold fluctuation Fig. I O  y -Cascade NMOS current mirror circuit. Figure I 1  shows the J(t,fi variation on an output voltage change (the voltage at the drain o f  MI) of 0.5V. The variation is minimal, suggesting that ‘atomistic’ fluctuations do not significantly affect device output resistance in saturation. 6 2. al e t $ 4  2 0 1.0 1.2 1.4 1.6 1.8 2.0 2.2 AI (%) Fig. I I I,,?,, variation distribution on a V,,,,, change ofO.SV, far Cascode NMOS current mirror. AI (%) . Fig. I2 Mismatch between b,, and /,,,,, distribution for Cascode NMOS current mirror. . .  . However, transistor matching through V, is critical for analogue circuit design, and fluctuations will .introduce pronounced mismatch between macroscopically identical devices. Figure 12 clearly shows this effect; the We have presented a methodology for integrating the results of ‘atomistic’ parameter fluctuations into compact model ensembles, for investigation of  analogue and digital circuits using devices in the nanometre regime. This methodology will allow analysis of the effects of a range of ‘atomistic’ phenomena - both singly and in combination -on circuits and systems. We have shown examples of this methodology applied to CMOS inverter and ring oscillator circuits, and to an analogue NMOS current mirror. [ I ]  T. Mizuno, J .  Okamura, A. Toriumi, “Experimental study of threshold voltage fluctuation due to statistical variation of  channel dopant number in MOSFETs”, IEEE Trans. Electron Devices vol. 41, pp. 2216-2221,1994 [2] A. Asenov, “3D statistical simulation of  intrinsic fluctuations in decanano MOSFETs induced by discrete dopants, oxide thickness fluctuations and LER“,  Proc. SISPAD2001, pp. 162-169,2001 [3] A. Asenov and S. Saini, “Suppression of random dopant-induced threshold voltage fluctuations in sub-0.1-pm MOSFET’s with epitaxial and delta - doped channels,” IEEE Transactions on Electron Devices, vol. 46, pp. 1718-24, 1999. [4] J.  A.  Croon, E. Augendre, el al., “Influence of Doping Profile and Halo Implantation on the Threshold Voltage Mismatch of a 0.13 pm CMOS Technology”, Proc. ESSDERC, pp. 579-582,2002 [51 H. P. Tuinhout, “Impact of parametric mismatch and fluctuations on performance and yield of deep- submicron CMOS technologies”, Proc. ESSDERC, pp, 95-101,2002 [6] P. A. Stolk, H. P. Tuinhout, et al., “CMOS Device Optimization for Mixed-Signal Technologies”, Tech. Digest IEDM, pp. 215-218,2OOl [7] A. Asenov, M. Jaraiz, S. Roy, G. Roy, et al., “Integrated Atomistic. Process and Device Simulation of Decananometre MOSFETs”, Proc. SISPAD2002, pp. 87-90,2002 [SI S. Inaba, K .  Okano, S. Matsuda, M. Fujiwara, et al., “High Performance 35 nm Gate Length CMOS with NO Oxynitride Gate Dielectric and Ni SALICIDE, Tech. Digest IEDM, 2001 

http://eprints.gla.ac.uk/2999/1/atomistic2_model_circuit.pdf

Integrating 'atomistic', intrinsic parameter fluctuations into compact model circuit analysis

Abstract

Similar works

Full text

Available Versions

Enlighten: Publications

Enlighten

Enlighten