Switched-Current Chaotic Neurons

The Letter presents two nonlinear CMOS current-mode circuits that implement neuron soma equations for chaotic neural networks. They have been fabricated in a double-metal, single-poly 1.6µm CMOS technology. The neuron soma circuits use a novel, highly accurate CMOS circuit strategy to realise piecewise-linear characteristics in the current-mode domain. Their prototypes obtain reduced area and low voltage power supply (down to 3V) with a clock frequency of 500 kHz

A 64-channel inductively-powered neural recording sensor array

This paper reports a 64-channel inductively powered neural recording sensor array. Neural signals are acquired, filtered, digitized and compressed in the channels. Additionally, each channel implements a local auto-calibration mechanism which configures the transfer characteristics of the recording site. The system has two operation modes; in one case the information captured by the channels is sent as uncompressed raw data; in the other, feature vectors extracted from the detected neural spikes are transmitted. Data streams coming from the channels are serialized by an embedded digital processor and transferred to the outside by means of the same inductive link used for powering the system. Simulation results show that the power consumption of the complete system is 377μW.Ministerio de Ciencia e Innovación TEC2009-0844

CMOS current-mode chaotic neurons

This paper presents two nonlinear CMOS current-mode circuits that implement neuron soma equations for chaotic neural networks, and another circuit to realize programmable current-mode synapse using CMOS-compatible BJT's. They have been fabricated in a double-metal, single-poly 1.6 /spl mu/m CMOS technology and their measured performance reached the expected function and specifications. The neuron soma circuits use a novel, highly accurate CMOS circuit strategy to realize piecewise-linear characteristics in the current-mode domain. Their prototypes obtain reduced area and low voltage power supply (down to 3 V) with clock frequency of 500 kHz. As regard to the synapse circuit, it obtains large linearity and continuous, linear, weight adjustment by exploration of the exponential-law operation of CMOS-BJT's. The full accordance observed between theory and measurements supports the development of future analog VLSI chaotic neural networks to emulate biological systems and advanced computation

Integrated chaos generators

This paper surveys the different design issues, from mathematical model to silicon, involved on the design of integrated circuits for the generation of chaotic behavior.Comisión Interministerial de Ciencia y Tecnología 1FD97-1611(TIC)European Commission ESPRIT 3110

CMOS design of chaotic oscillators using state variables: a monolithic Chua's circuit

This paper presents design considerations for monolithic implementation of piecewise-linear (PWL) dynamic systems in CMOS technology. Starting from a review of available CMOS circuit primitives and their respective merits and drawbacks, the paper proposes a synthesis approach for PWL dynamic systems, based on state-variable methods, and identifies the associated analog operators. The GmC approach, combining quasi-linear VCCS's, PWL VCCS's, and capacitors is then explored regarding the implementation of these operators. CMOS basic building blocks for the realization of the quasi-linear VCCS's and PWL VCCS's are presented and applied to design a Chua's circuit IC. The influence of GmC parasitics on the performance of dynamic PWL systems is illustrated through this example. Measured chaotic attractors from a Chua's circuit prototype are given. The prototype has been fabricated in a 2.4- mu m double-poly n-well CMOS technology, and occupies 0.35 mm/sup 2/, with a power consumption of 1.6 mW for a +or-2.5-V symmetric supply. Measurements show bifurcation toward a double-scroll Chua's attractor by changing a bias current

Design considerations for integrated continuous-time chaotic oscillators

This paper presents an optimization procedure to choose the chaotic state equation which is best suited for implementation using Gm-C integrated circuit techniques. The paper also presents an analysis of the most significant hardware nonidealities of Gm-C circuits on the chaotic operation-the basis to design robust integrated circuits with reproducible and easily controllable behavior. The techniques in the paper are illustrated through a circuit fabricated in 2.4-/iin double-poly technology.Comisión Interministerial de Ciencia y Tecnología TIC 96-1392-CO2-

A power efficient neural spike recording channel with data bandwidth reduction

This paper presents a mixed-signal neural spike recording channel which features, as an added value, a simple and low-power data compression mechanism. The channel uses a band-limited differential low noise amplifier and a binary search data converter, together with other digital and analog blocks for control, programming and spike characterization. The channel offers a self-calibration operation mode and it can be configured both for signal tracking (to raw digitize the acquired neural waveform) and feature extraction (to build a first-order PWL approximation of the spikes). The prototype has been fabricated in a standard CMOS 0.13μm and occupies 400μm×400μm. The overall power consumption of the channel during signal tracking is 2.8μW and increases to 3.0μW average when the feature extraction operation mode is programmed.Ministerio de Ciencia e Innovación TEC2009-08447Junta de Andalucía TIC-0281