Space Complexity of Perfect Matching in Bounded Genus Bipartite Graphs

We investigate the space complexity of certain perfect matching problems over bipartite graphs embedded on surfaces of constant genus (orientable or non-orientable). We show that the problems of deciding whether such graphs have (1) a perfect matching or not and (2) a unique perfect matching or not, are in the logspace complexity class \SPL. Since \SPL\ is contained in the logspace counting classes \oplus\L (in fact in \modk\ for all $k\geq 2$), \CeqL, and \PL, our upper bound places the above-mentioned matching problems in these counting classes as well. We also show that the search version, computing a perfect matching, for this class of graphs is in \FL^{\SPL}. Our results extend the same upper bounds for these problems over bipartite planar graphs known earlier. As our main technical result, we design a logspace computable and polynomially bounded weight function which isolates a minimum weight perfect matching in bipartite graphs embedded on surfaces of constant genus. We use results from algebraic topology for proving the correctness of the weight function.Comment: 23 pages, 13 figure

Robustness of Power Analysis Attack Resilient Adiabatic Logic: WCS-QuAL under PVT Variations

In this paper, we propose Without Charge Sharing Quasi Adiabatic Logic (WCS-QuAL) as a countermeasure against Power Analysis Attacks. We evaluate and compare our logic with the recently proposed secure adiabatic logic designs SPGAL and EE-SPFAL at frequencies ranging from 1MHz to 100MHz. Simulation results show that WCS-QuAL outperforms the existing secure adiabatic logic designs on the basis of % Normalized Energy Deviation (NED) and % Normalized Standard Deviation (NSD) at all simulated frequencies. Also, all 2-input gates using WCS-QuAL dissipate nearly equal energy for all possible input transitions. In addition, the energy dissipated by WCS-QuAL approaches to the energy dissipation of EESPFAL and SPGAL as the output load capacitance is increased above 100fF. To further evaluate and compare the performance, GF (24) bit-parallel multiplier was implemented as a design example. The impact of Process-Voltage-Temperature (PVT) variations, power supply scaling and technology on the performance of the three logic designs was investigated and compared. Simulation results show that WCS-QuAL passed the functionality test against PVT variations and can perform well against the power supply scaling (from 1.8V to 0.5V). It also exhibits the least value of %NED and %NSD against PVT variations and when the power supply is scaled down compared to EE-SPFAL and SPGAL. At lower technology, WCS-QuAL, shows more improvement in energy dissipation than EE-SPFAL

Energy efficiency of 2- Step power-clocks for adiabatic logic

The generation of power-clocks in adiabatic integrated circuits is investigated. Specifically, we consider the energy efficiency of a 2-step charging strategy based on a single tank-capacitor circuit. We have investigated the impact of various parameters such as tank-capacitance to load capacitance ratio, ramping time, transistors sizing and power supply voltage scaling on energy recovery achievable in the 2-step charging circuit. We show that energy recovery achievable in the 2-step charging circuit depends on the tank-capacitor and load capacitor size concluding that tank-capacitance (CT) versus load capacitance (CL) is the significant parameter. We also show that the energy performance depends on the ramping time and improves for higher ramping times (lower frequencies). Energy recovery also improves if the transistors sizes in the step charging circuit are sized at their minimum dimensions. Lastly, we show that energy recovery decreases as the power supply voltage is scaled down. Specifically, the decrease in the energy recovery with decreasing power supply is significant for lower ramping times (higher frequencies). We propose that a Ct/Cl ratio of 10, keeping the width of the transistors in the step charging circuit minimum, can be chosen as a convenient `rule-of-thumb' in practical designs

Symmetric Power Analysis Attack Resilient Adiabatic Logic for Smartcard Applications

On the whole existing secure adiabatic logic designs exhibit variations in current peaks and have asymmetric structures. However, asymmetric structure and variations in current peaks make the circuit vulnerable to Power Analysis Attacks (PAA). In this paper, we shall present a novel PAA resilient adiabatic logic which has a symmetric structure and exhibits the least variations in current peaks for basic gates as well as in 8-bit Montgomery multiplier. The proposed logic has been compared with two recently proposed secure adiabatic logic designs for operating frequencies ranging from 1MHz to 100MHz and power-supply scaling ranging from 0.6V to 1.8V. Simulation results of the gates show that our proposed logic exhibits the lowest Normalized Energy Deviation (NED) and Normalized Standard Deviation (NSD) under the said frequency variations. All the 2-input gates that deploy the proposed logic dissipate nearly the same average energy within 0.2% of each other at all the frequencies simulated and thus, along with the dataindependence,gate-function-independence is achieved. The paper will also report on the energy dissipated by the proposed logic which approaches that of the existing logic designs as the output load capacitance is increased above 100fF. The simulation results of the 8-bit adiabatic Montgomery multiplier show that the proposed logic exhibits the least value of NED and NSD under the said frequency variations and power-supply scaling. Finally, the paper will report on the current waveform graphs for variations in current peaks under power-clock scaling

Investigation of Stepwise Charging Circuits for Power-Clock Generation in Adiabatic Logic

The generation of power-clocks in adiabatic integrated circuits is investigated. Specifically, we consider stepwise charging strategies (2, 3, 4, 5, 6, 7, and 8-step) based on tank-capacitor circuits, comparing them in terms of their energy recovery properties and complexity. We show that energy recovery achievable depends on the tank-capacitor size. We also show that tank-capacitor sizes can be reduced as their number increases concluding that combined tank capacitance (CTT) versus load capacitance (CL) ratio is the significant parameter. We propose that using a CTT/CL ratio of 10 and using a 4-step charging power-clock constitute appropriate trade-offs in practical circuits

A Novel Power Analysis Attack Resilient Adiabatic Logic without Charge Sharing

In this paper, we propose a novel power analysis attack resilient adiabatic logic which, unlike existing secure adiabatic logic designs doesn’t require any charge sharing between the output nodes of the gates. The proposed logic also removes the non-adiabatic losses (NAL) during the evaluation phase of the power-clock. We investigate and compare our proposed and the existing secure adiabatic logic across a range of “power-clock” frequencies on the basis of percentage Normalized Energy Deviation (%NED), percentage Normalized Standard Deviation(%NSD) and average energy dissipation. The pre-layout and post-layout simulation results show that our proposed logic exhibits the least value of %NED and %NSD in comparison to the existing secure adiabatic logic designs at the frequency ranging from 1MHz to 100MHz. Also, our proposed logic consumes the lowest energy

Investigating the effectiveness of Without Charge-Sharing Quasi-Adiabatic Logic for energy efficient and secure cryptographic implementations

Existing secure adiabatic logic designs use charge sharing inputs to deliver input independent energy dissipation and suffer from non-adiabatic losses (NAL) during the evaluation phase of the power-clock. However, using additional inputs present the overhead of generation, scheduling, and routing of the signals. Thus, we present “Without Charge-Sharing Quasi-Adiabatic Logic”, WCS-QuAL which doesn't require any charge sharing inputs and completely removes the NAL. The pre-layout and post-layout simulation results of the gates show that WCS-QuAL exhibits the lowest Normalized Energy Deviation (NED) and Normalized Standard Deviation (NSD) against all process corner variations at frequencies ranging from 1 MHz to 100 MHz. It also shows least variations in average energy dissipation at all five process corners. The simulation results show that the 8-bit Montgomery multiplier using WCS-QuAL exhibits the least value of NED and NSD at all the simulated frequencies and against power-supply scaling and dissipates the lowest energy at frequencies ranging from 20 MHz to 100 MHz

Equipartition of Current in Parallel Conductors on Cooling Through the Superconducting Transition

Our experiments show that for two or more pieces of a wire, of different lengths in general, combined in parallel and connected to a dc source, the current ratio evolves towards unity as the combination is cooled to the superconducting transition temperature Tc, and remains pinned at that value below it. This re-distribution of the total current towards equipartition without external fine tuning is a surprise. It can be physically understood in terms of a mechanism that involves the flux-flow resistance associated with the transport current in a wire of type-II superconducting material. It is the fact that the flux-flow resistance increases with current that drives the current division towards equipartition.Comment: Revised version of J.Phys. Condens.Matter; vol. 18(2006) L143-L147 14 pages including 3 figures; provided an explanation in terms of the physical mechanism of flux flow induced resistance that is proportional to the impressed current. We are adding a simple, physically robust derivation of our equipartition without taking resort to the minimum dissipation principl

Information Risk Communication in the Context of Zika Virus: A Pilot Study

Dissemination of information to at-risk populations is essential in any emergency situation. Among many health emergencies, Zika virus is a large-scale health challenge that requires authorities to communicate the risks of the virus, and, potential protective measures to the population. Communication technologies have an important role to play in this effort. Other factors, such as hazard characteristics and warning fatigue, also influence the effectiveness of communication. This article develops an adaptation of the Protective Action Decision Making (PADM) model for a holistic understanding of the technical and non-technical factors that influence the responses of vulnerable individuals to information about the Zika virus. The findings are expected to provide practical guidance to public health agencies in the selection of appropriate mix of media to deliver information about Zika. Investigation of antecedents to vulnerable stakeholders’ response will contribute to the growing literature on information risk communication and emergency responses to potential epidemics

Structural basis of mitochondrial receptor binding and constriction by DRP1.

Mitochondrial inheritance, genome maintenance and metabolic adaptation depend on organelle fission by dynamin-related protein 1 (DRP1) and its mitochondrial receptors. DRP1 receptors include the paralogues mitochondrial dynamics proteins of 49 and 51 kDa (MID49 and MID51) and mitochondrial fission factor (MFF); however, the mechanisms by which these proteins recruit and regulate DRP1 are unknown. Here we present a cryo-electron microscopy structure of full-length human DRP1 co-assembled with MID49 and an analysis of structure- and disease-based mutations. We report that GTP induces a marked elongation and rotation of the GTPase domain, bundle-signalling element and connecting hinge loops of DRP1. In this conformation, a network of multivalent interactions promotes the polymerization of a linear DRP1 filament with MID49 or MID51. After co-assembly, GTP hydrolysis and exchange lead to MID receptor dissociation, filament shortening and curling of DRP1 oligomers into constricted and closed rings. Together, these views of full-length, receptor- and nucleotide-bound conformations reveal how DRP1 performs mechanical work through nucleotide-driven allostery