A very-front-end ADC for the electromagnetic calorimeter of the International Linear Collider

A 10-bits pipeline Analog-to-Digital Converter (ADC) is introduced in this paper and the measurements carried out on prototypes produced in a 0.35 µm CMOS technology are presented. This ADC is a building block of the very-front-end electronics dedicated to the electromagnetic calorimeter of the International Linear Collider (ILC). Based on a 1.5-bit resolution per stage architecture, it reaches the 10-bits precision at a sampling rate of 4 MSamples/s with a consumption of 35 mW. Integral and Differential Non-Linearity obtained are respectively within ±1 LSB and ±0.6 LSB, and the measured noise is 0.47 LSB at 68% C.L. The performance obtained confirms that the pipeline architecture ADC is suitable for the Ecal readout requirement

The mixed analog/digital shaper of the LHCb preshower

The LHCb preshower signals show so many fluctuations at low energy that a classical shaping is not usable at all. Thanks to the fact that the fraction of the collected energy during a whole LHC beam crossing time is 85%, we studied the special solution we presented at Snowmass 1999 workshop. This solution consists of 2 interleaved fast integrators, one being in integrate mode when the other is digitally reset. Two track-and-hold systems and an analog multiplexer are used to give at the output 85% of the signal plus 15% of the previous one. These 15% are digitally computed from the previous sample, and subtracted. A completely new design of this solution had to be made. This new design is described, including new methods to decrease the supply voltage and the noise, as well as to increase the quality of the reset and the linearity. An output stage, consisting of an AB class push-pull using only NPN transistors is also described. Laboratory and beam test results are given. (5 refs)

Level 0 trigger decision unit for the LHCb experiment

The Level-0 Decision Unit (L0DU) is the central part of the first trigger level of the LHCb detector. The L0DU receives information from the Calorimeter, Muon and Pile-Up sub-triggers, with fixed latencies, at 40 MHz via 24 high speed optical fiber links running at 1.6 Gb/s. The L0DU performs simple physics algorithm to compute the decision in order to reduce the data flow down to 1 MHz for the next trigger level and a L0Block is constructed. The processing is implemented in FPGA using a 40 MHz synchronous pipelined architecture. The algorithm can be easily configured with the Experiment Control System (ECS) without FPGA reprogramming. The L0DU is a 16 layer custom board

LHCb Preshower Front-End Electronics Board. Qualification of the final prototype

This note describes the tests performed on the final prototypes of the SPD/Preshower Front-End electronics boards

A mixed analog/digital shaper for the LHCb preshower

This note describes, first, the experimental and theoretical studies of the LHCb's preshower signals performed with a prototype cell. Four designs of the very front end electronic are then discuted and a choice is proposed

LHCb Preshower Front-End Electronics Board

This note describes the digital part of the fully synchronous solution developped for the lhcb preshower detector Front-End electronics. The general design and the main features of this board are given including trigger part