3,190 research outputs found

    Efficient state reduction methods for PLA-based sequential circuits

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    Experiences with heuristics for the state reduction of finite-state machines are presented and two new heuristic algorithms described in detail. Results on machines from the literature and from the MCNC benchmark set are shown. The area of the PLA implementation of the combinational component and the design time are used as figures of merit. The comparison of such parameters, when the state reduction step is included in the design process and when it is not, suggests that fast state-reduction heuristics should be implemented within FSM automatic synthesis systems

    Efficient realization of a threshold voter for self-purging redundancy

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    The self-purging technique is not commonly used mainly due to the lack of practical implementations of its key component, the threshold voter. A very efficient implementation of this voter is presented which uses a decomposition technique to substantially reduce the circuit complexity and delay, as compared to alternative implementations.Comisión Interministerial de Ciencia y Tecnología TIC97-064

    RTD based logic circuits using generalized threshold gates

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    Many logic circuit applications of Resonant Tunneling Diodes are based on the MOnostable-BIstable Logic Element (MOBILE). Threshold logic is a computational model widely used in the design of MOBILE circuits, i.e. these circuits are built from threshold gates (TGs). The MOBILE realization of generalized threshold gates is being investigated. Multi-Threshold Threshold Gates (MTTGs) have been proposed which further increase the functionality of the original TGs. Recently, we have proposed a novel MOBILE circuit topology obtained by fundamental properties of threshold functions. This paper describes the design of n-bit adders using these novel MOBILE circuit topologies. A comparison with designs based on TGs and MTTGs is carried out showing advantages in terms of speed and power delay product and device counts.España, Gobierno TEC2007-67245Junta de Andalucía EXC/2007/TIC-296

    Two-phase RTD-CMOS pipelined circuits

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    MOnostable-BIstable Logic Element (MOBILE) networks can be operated in a gate-level pipelined fashion (nanopipeline) allowing high through output. Resonant tunneling diode (RTD)-based MOBILE nanopipelined circuits have been reported using different clock schemes including a four-phase strategy and a single-phase clock scheme. In particular, significant power advantages of single-phase RTD-CMOS MOBILE circuits over pure CMOS have been shown. This letter compares the RTD-CMOS realizations using a single clock and a novel two-phase clock solution. Significant superior robustness and performance in terms of power and area are obtained for the two-phase implementations

    Acto de contrición de Santa Teresa de Jesús [Música impresa]: motete al Sagrado Corazón de Jesús para soprano o tenor con acompañamiento de harmonium

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    En la port.: Aprobada por la Junta Censora de Música Sacra del Obispado de Barcelona.Copia digital : Junta de Castilla y León. Consejería de Cultura y Turismo, 201

    Intracerebral haemorrhage in a dog with steroid-responsive meningitis arteritis

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    A one-year and six-month-old female neutered Boxer dog was presented with a four-day history of pyrexia, lethargy and neck pain. An intracerebral haemorrhage and a mediastinal mass were identified. Cerebrospinal fluid analysis revealed severe neutrophilic pleocytosis, and steroid-responsive meningitis arteritis (SRMA) was suspected. A significant improvement was observed with immunosuppressive steroid therapy and subsequent imaging revealed a reduction in size of the intracerebral haemorrhage and disappearance of the mediastinal mass. SRMA is a systemic disease with potential involvement of multiple organs. Intracerebral haemorrhage can occur secondary to SRMA and can have a successful outcome

    Sorting networks implemented as νMOS circuits

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    A new realisation for n-input sorters is presented. Resorting to the neuron-MOS (νMOS) concept and to an adequate electrical scheme, a compact and efficient implementation is obtained.Comisión Interministerial de Ciencia y Tecnología TIC95-0094, TIC97-064
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